EPC635 datasheet(19/97 Pages) EPC

19 / 97 page

epc635 is supplied with four positive (+1.8V, +2.5/3.3V, +5V, +10V) and one negative (VBS) external DC supply voltage levels (Figure 14).

■ Decoupling capacitors must be placed next to each supply pin pair in order to minimise the instantaneous voltage drop on internal supply

rails due to fast switching high-speed signals (Table 10). They help reducing switching noise on internal/external supply rails. Therefore,

they minimize the impact on system's optical/electrical performance.

+1.8V is used for supplying the digital logic (VDD), the on-chip oscillator OSC and the phase-look-loop PLL (VDDPLL).

■ The digital logic creates some internal switching noise on VDD.

■ When same supply is shared together with OSC and PLL, their supply wiring must be separated from the digital wires and physically

isolated from each other. These supplies are marked in the application diagram as VDD and VDDPLL, respectively (Figure 14). A good

practice is inserting on the PCB a series inductance of 100nH between them close to the supply source, then creating separate supply

islands for both on the board. The XTAL/OSC and PLL are critical parts of the chip which directly impacts the optical system perform -

ance (i.e. distance calculation). Therefore, if the +1.8V supply is too noisy, it is recommended for the application to have a dedicated si-

lent +1.8V supply only for OSC and PLL.

+2.5/3.3V is used for supplying the high-speed IO pins (TCMI and LED2) and the slow I2C pins (VDDIO).

■ High speed IO pins toggle at 10/20/40/80MHz during data transfer, hence generating continuously switching noise (much more dominant

than the digital noise). Therefore VDDIO supply wires and layers must be carefully designed and isolated in a separate supply island on

the PCB.

■ I2C pins external pull-up resistors can share the same supply on the PCB.

■ As the name implies, the IO supply voltage can be one of the two +2.5V, +3.3V or in between. The specific IO voltage depends on the

choice of the application CPU's IO voltage and other system supply requirements. It is not recommend to change this voltage on the fly

when the TCMI, LED2 or I2C interfaces are running. When the application needs power saving during system idle periods, it can be

scaled from +3.3V down to +2.5V only after frame acquisition is stopped and both interfaces are completely inactivated. It can be in-

creased back to +3.3V before re-activating the chip for frame acquisition, accessing I2C, LED2 or TCMI interface. Note that, voltage scal-

ing must be done in a controlled way having both application CPU's and epc635's IO voltages at the same time at the same level.

■ Some CPU's can also work at +2.5V IO voltage but with reduced IO toggle speed. In such situations, application must make sure that

the right TCMI DCLK frequency is set, both on the epc635 and on the CPU itself.

+5V is used for supplying analog blocks of the chip e.g. pixel-field drivers and ADC readout circuitry. Refer to Figure 14).

■ It needs a dedicated supply to keep it biased at this voltage.

+10V is used for supplying pixel-field circuitry (VDDPXH).

■ It needs a dedicated supply to keep it biased at this voltage.

VBS is used for biasing the the pixel-field.

■ The use of a stable supply source with a low ripple is recommended. There is no switching or active internal circuit dependent current

consumption. But, an ambient-light dependent leakage current is generated on this pin and therefore it needs a dedicated supply to keep

it biased at this voltage (refer to Table 1, note 8).

A 4MHz quartz crystal or a ceramic resonator together with two load capacitors must be connected to XTALIN_CLKIN and XTALOUT pins

in order to use internal oscillator OSC as time base for the epc635. The load capacitor value has to be selected according the crystal or

resonator supplier's recommendation. The frequency accuracy and stability are directly related to the distance readings. Alternatively an

external clock source can be connected to XTALIN_CLKIN pin, leaving XTALOUT unconnected (chapter 5.2.).

The optional MODCLK input can be used for user controlled/modulated clock. It is used for both the LED driver and the pixel-field demodu -

lator.

SCL, SDA are I2C slave pins which need external pull-up resistors on the PCB (see also VDDIO supply). Values of R16 and R17 are given

only for indicative purposes and must be re-calculated according to the total capacitive load of all I 2C slave/master devices and the operat-

ing mode FM or FM+ of the I2C (chapter 5.4.) in the application.

VSYNC_A0, HSYNC_A1, XSYNC_SAT_CFG, DATA[11:0], DCLK, high-speed TCMI signals (chapter 5.9.), SHUTTER and RESET control

signals toggle in the VDDIO range.

■ To minimize the skew, the high-speed *SYNC, DATA[11:0], DCLK signals wires must be routed equal in impedance and length less than

10cm long with less than 10mm difference on the PCB. As they are toggling all the time, they can be separated with ground wires on the

side adjacent to other signals/supply lines, routed with enough distance from other sensitive signal wires on the board. Series termina-

tion resistors R4 … R15 (10 … 33Ω) are needed at high-speed outputs to control the slew.

■ They must be directly connected to the application CPU. In some cases RESET can also be driven from power management device.

■ There are optional pull-up resistors R19 and R19 (10kΩ) to set initial values of some configuration registers during start up of the chip.

Such outputs pins are called strap pins. They are scanned one time immediately after RESET is released (chapter 5.3.3.). Two LSB of

the I2C device address bits are programmable via these strap pins during start-up (chapter 5.3.). When there is only one slave and one

master on the I2C bus as in the application diagram (Figure 14), these resistors can be omitted.

Characteristics subject to change without notice

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