R5F11BLE datasheet(133/143 Pages) RENESAS

133 / 143 page

RL78/G1F

3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)

R01DS0246EJ0110 Rev. 1.10

Page 133 of 140

Aug 12, 2016

3.6.8

Power supply voltage rising slope characteristics

Caution

Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating

voltage range shown in 3.4 AC Characteristics.

3.7

RAM Data Retention Characteristics

Note 1.

The value depends on the POR detection voltage. When the voltage drops, the RAM data is retained before a POR reset

is effected, but RAM data is not retained when a POR reset is effected.

Note 2.

Enter STOP mode before the supply voltage falls below the recommended operating voltage.

3.8

Flash Memory Programming Characteristics

(2)

Interrupt & Reset Mode

(TA = -40 to +105°C, VPDR

≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Voltage detection

threshold

VLVDD0

VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage

2.64

2.75

2.86

VLVDD1

LVIS1, LVIS0 = 1, 0

Rising release reset voltage

2.81

2.92

3.03

Falling interrupt voltage

2.75

2.86

2.97

VLVDD2

LVIS1, LVIS0 = 0, 1

Rising release reset voltage

2.90

3.02

3.14

Falling interrupt voltage

2.85

2.96

3.07

VLVDD3

LVIS1, LVIS0 = 0, 0

Rising release reset voltage

3.90

4.06

4.22

Falling interrupt voltage

3.83

3.98

4.13

(TA = -40 to +105°C, VSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Power supply voltage rising slope

SVDD

V/ms

(TA = -40 to +105°C, VSS = 0V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Data retention supply voltage

VDDDR

1.44 Notes 1, 2

5.5

(TA = -40 to +105°C, 2.4 V

≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

System clock frequency

fCLK

2.4 V

≤ VDD ≤ 5.5 V

MHz

VDD

STOP instruction execution

Standby release signal

(interrupt request)

STOP mode

RAM data retention

Operation mode

VDDDR

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