R5F564MFDDFB datasheet(142/228 Pages) RENESAS

142 / 228 page

R01DS0173EJ0110 Rev.1.10

Page 142 of 228

Oct 24, 2016

RX64M Group

5. Electrical Characteristics

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. Supply of the clock signal to peripheral modules is stopped in this state. This does not include operations as BGO (background

operations).

Note 3. ICC depends on f (ICLK) as follows. (ICLK/PCLKA:PCLKB/PCLKC/PCLKD:BCLK:BCLK pin = 10:5:10:5 when EXTAL = 12 MHz)

ICC Max. = 0.77 × f + 18 (max. operation in high-speed operating mode)

ICC Typ. = 0.08 × f + 6 (normal operation in high-speed operating mode)

ICC Typ. = 0.5 × f + 2.6 (low-speed operating mode 1)

ICC Max. = 0.36 × f + 18 (sleep mode)

Note 4. This does not include operations as BGO (background operations). Whether supply of the clock signal to peripheral modules

continues or is stopped only depends on the state determined by the settings of the bits in module stop control registers A to D.

The setting for the peripheral module clock stopped state is FCLK = BCLK = PCLKA = PCLKB = PCLKC = PCLKD = BCLK pin

= 3.75 MHz (division by 64).

Note 5. This is the increase for programming or erasure of the code flash memory (limitations apply to the combinations of ranges in

which writing proceed) or data flash memory during program execution in the code flash memory.

Note 6. The low power consumption function is disabled and DEEPCUT[1:0] = 01b.

Note 7. The low power consumption function is enabled and DEEPCUT[1:0] = 11b.

Table 5.4

DC Characteristics (3)

Conditions: VCC = AVCC0 = AVCC1 = VREFH0 = VCC_USB = 2.7 to 3.6 V, 2.7

≤ VREFH0 ≤ AVCC0,

VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,

Ta = Topr

Item

Symbol

Min.

Typ.

Max.

Unit

Test Conditions

Supply

current*1

Max.*2

ICC*3

—

110

ICLK = 120 MHz

PCLKA = 120 MHz

PCLKB = 60 MHz

PCLKC = 60 MHz

PCLKD = 60 MHz

FCLK = 60 MHz

BCLK = 120 MHz

BCLK pin = 60 MHz

Normal

Peripheral function clock signal

supplied*4

—39

—

Peripheral function clock signal

stopped*4

—16

—

Coremark Peripheral function clock signal

stopped*4

—21

—

Sleep mode: Supply of the clock signal to

peripheral modules is stopped*4

All-module-clock-stop mode (reference value)

—

Increased

by BGO

operation

Reading from the code flash memory

while the data flash memory is being

programmed

—7

—

Reading from the code flash memory

while the code flash memory is being

programmed

—10

—

Low-speed operating mode 1: Supply of the clock signal

to peripheral modules is stopped*4

—

All clocks 1 MHz

Low-speed operating mode 2: Supply of the clock signal

to peripheral modules is stopped*4

—

1.2

—

All clocks 32.768 kHz

Software standby mode

—

0.7

Power supplied to standby RAM and USB resume

detecting unit (USB0 only)

—22

μA

Power not

supplied to

standby RAM and

USB resume

detecting unit

(USB0 only)

Power-on reset circuit and low-

power consumption function

disabled*6

—

12.5

Power-on reset circuit and low-

power consumption function

enabled*7

—

3.1

13.5

Increased by

RTC operation

When a crystal resonator for

low clock loads is in use

—0.6

—

When a crystal resonator for

standard clock loads is in use

—2.0

—

RTC operating while

VCC is off (with the

battery backup

function, only the RTC

and sub-clock

oscillator operate)

When a crystal resonator for

low clock loads is in use

—0.9

—

VBATT = 2.0 V,

VCC = 0 V

—1.6

—

VBATT = 3.3 V,

VCC = 0 V

When a crystal resonator for

standard clock loads is in use

—1.7

—

VBATT = 2.0 V,

VCC = 0 V

—3.3

—

VBATT = 3.3 V,

VCC = 0 V

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