R5F564MFDDFB datasheet(138/228 Pages) RENESAS

138 / 228 page

R01DS0173EJ0110 Rev.1.10

Page 138 of 228

Oct 24, 2016

RX64M Group

4. I/O Registers

Note 1. When the same output trigger is specified for pulse output groups 2 and 3 by the PPG0.PCR setting, the PPG0.NDRH address

is 0008 81ECh. When different output

triggers are specified, the PPG0.NDRH addresses for pulse output groups 2 and 3 are 0008 81EEh and 0008 81ECh,

respectively.

Note 2. When the same output trigger is specified for pulse output groups 0 and 1 by the PPG0.PCR setting, the PPG0.NDRL address

is 0008 81EDh. When different output

triggers are specified, the PPG0.NDRL addresses for pulse output groups 0 and 1 are 0008 81EFh and 0008 81EDh,

respectively.

Note 3. When the same output trigger is specified for pulse output groups 6 and 7 by the PPG1.PCR setting, the PPG1.NDRH address

is 0008 81FCh. When different output

triggers are specified, the PPG1.NDRH addresses for pulse output groups 6 and 7 are 0008 81FEh and 0008 81FCh,

respectively.

Note 4. When the same output trigger is specified for pulse output groups 4 and 5 by the PPG1.PCR setting, the PPG1.NDRL address

is 0008 81FDh. When different output

triggers are specified, the PPG1.NDRL addresses for pulse output groups 4 and 5 are 0008 81FFh and 0008 81FDh,

respectively.

Note 5. When the register is accessed while the USB is operating, a delay may be generated in accessing.

Note 6. The address must end with 0h, 4h, 8h, or Ch when access is made in 32-bit units. The address must end with 0h, 2h, 4h, 6h, 8h,

Ah, Ch, or Eh when access is made in 16-bit units.

000D 0548h

USBA

Host L1 Control Register 1

HL1CTRL1

(3 + BUSWAIT)

PCLKA or more

Rounded up to the

nearest integer

greater than 1 + (3 +

BUSWAIT) × (fre-

quency ratio of ICLK/

PCLKB)*5

USBA

000D 054Ah

USBA

Host L1 Control Register 2

HL1CTRL2

(3 + BUSWAIT)

PCLKA or more

Rounded up to the

nearest integer

greater than 1 + (3 +

BUSWAIT) × (fre-

quency ratio of ICLK/

PCLKB)*5

USBA

000D 0560h

USBA

Deep Standby USB Transceiver Control/Pin Monitor

DPUSR0R

(3 + BUSWAIT)

PCLKA or more

Rounded up to the

nearest integer

greater than 1 + (3 +

BUSWAIT) × (fre-

quency ratio of ICLK/

PCLKB)*5

USBA

000D 0564h

USBA

Deep Standby USB Suspend/Resume Interrupt

DPUSR1R

(3 + BUSWAIT)

PCLKA or more

Rounded up to the

nearest integer

greater than 1 + (3 +

BUSWAIT) × (fre-

quency ratio of ICLK/

PCLKB)*5

USBA

Table 4.1

List of I/O Registers (Address Order) (67 / 67)

Address

Module

Symbol Register Name

Symbol

Number

of Bits

Access

Size

Number of Access Cycles

Function

ICLK

PCLK

ICLK

 PCLK

R5F564MFDDFB Datasheet(PDF) 138 Page - Renesas Technology Corp

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