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CS4399 Datasheet(PDF) 71 Page - Cirrus Logic |
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CS4399 Datasheet(HTML) 71 Page - Cirrus Logic |
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71 / 111 page ![]() DS1113F1 71 CS4399 6 Register Quick Reference 0x06 0001 XSP Channel 2 Location XSP_RX_CH2 p. 83 0 000000 0 0x06 0002– 0x06 0009 Reserved — 0 000000 0 0x06 000A XSP Channel 1 Size and Enable — XSP_RX_ CH1_AP XSP_RX_ CH1_EN XSP_RX_CH1_RES p. 83 0 000011 0 0x06 000B XSP Channel 2 Size and Enable — XSP_RX_ CH2_AP XSP_RX_ CH2_EN XSP_RX_CH2_RES p. 83 0 000111 0 0x06 000C– 0x06 FFFF Reserved — 0 000000 0 0x07 0000 DSD Volume B DSD_VOLUME_B p. 84 0 111100 0 0x07 0001 DSD Volume A DSD_VOLUME_A p. 84 0 111100 0 0x07 0002 DSD Processor Path Signal Control 1 —DSD_VOL_ BEQA DSD_SZC — DSD_AMUTE DSD_AMUTE_ BEQA DSD_MUTE_A DSD_MUTE_B p. 84 1 010100 0 0x07 0003 DSD Interface Configuration — DSD_M_SB DSD_PM_EN DSD_PM_SEL p. 85 0 000000 0 0x07 0004 DSD Processor Path Signal Control 2 — DSD_PRC_SRC DSD_EN — DSD_SPEED STA_DSD_ DET INV_DSD_ DET p. 85 0 000001 0 0x07 0005 DSD and PCM Mixing Control —MIX_PCM_ PREP MIX_PCM_ DSD p. 85 0 000000 0 0x07 0006 DSD Processor Path Signal Control 3 DSD_ZERODB DSD_HPF_EN — SIGCTL_ DSDEQPCM DSD_INV_A DSD_INV_B DSD_SWAP_ CHAN DSD_COPY_ CHAN p. 86 0 100000 0 0x07 0008– 0x07 FFFF Reserved — 0 000000 0 0x08 0000 Analog Output Control 1 — — OUT_FS — — p. 86 0 011000 0 0x08 0001– 0x08 FFFF Reserved — 0 000000 0 0x09 0000 PCM Filter Option FILTER_ SLOW_FASTB PHCOMP_ LOWLATB NOS — HIGH_PASS DEEMP_ON p. 87 0 000001 0 0x09 0001 PCM Volume B PCM_VOLUME_B p. 87 0 111100 0 0x09 0002 PCM Volume A PCM_VOLUME_A p. 87 0 111100 0 0x09 0003 PCM Path Signal Control 1 PCM_RAMP_ DOWN PCM_VOL_ BEQA PCM_SZC PCM_AMUTE PCM_ AMUTEBEQA PCM_MUTE_A PCM_MUTE_B p. 88 1 010100 0 0x09 0004 PCM Path Signal Control 2 — PCM_INV_A PCM_INV_B PCM_SWAP_ CHAN PCM_COPY_ CHAN p. 88 0 000000 0 0x09 0005– 0x0A FFFF Reserved — 0 000000 0 0x0B 0000 Class H Control — ADPT_PWR HV_EN EXT_VCPFILT p. 89 0 001111 0 0x0B 0001– 0x0C FFFF Reserved — 0 000000 0 0x0D 0000 HP Detect HPDETECT_CTRL HPDETECT_ INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME — p. 89 0 000010 0 0x0D 0001 HP Status (Read Only) — HPDETECT_ PLUG_DBC HPDETECT_ UNPLUG_DBC — p. 89 0 000000 0 0x0D 0002– 0x0E 001A Reserved — 0 000000 0 0x0E 001B– 0x0E FFFF Reserved — 0 000000 0 Table 6-1. Register Quick Reference (Cont.) Address Function 7 654321 0 |
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