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TMS320DM6431 Datasheet(PDF) 60 Page - Texas Instruments |
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TMS320DM6431 Datasheet(HTML) 60 Page - Texas Instruments |
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60 / 227 page  3.2 Power Considerations TMS320DM6431 Digital Media Processor SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008 www.ti.com The DM6431 provides several means of managing power consumption. As described in the Section 6.3.4, DM6431 Power and Clock Domains, the DM6431 has one single power domain—the “Always On” power domain. Within this power domain, the DM6431 utilizes local clock gating via the Power and Sleep Controller (PSC) to achieve power savings. For more details on the PSC, see Section 6.3.5, Power and Sleep Controller (PSC) and the TMS320DM643x DMP DSP Subsystem Reference Guide (literature number SPRU978). Some of the DM6431 peripherals support additional power saving features. For more details on power saving features supported, see the TMS320DM643x DMP Peripherals Overview Reference Guide (literature number SPRU983). Most DM6431 3.3-V I/Os can be powered-down to reduce power consumption. The VDD3P3V_PWDN register in the System Module (see Figure 3-1) is used to selectively power down unused 3.3-V I/O pins. For independent control, the 3.3-V I/Os are separated into functional groups—most of which are named according to the pin multiplexing groups (see Table 3-2). Only the I/O buffers in these groups are powered up by default: CLKOUT Block, EMIFA/VPSS Block, Host Block, and GPIO Block. Note: To save power, all other I/O buffers are powered down by default. Before using these pins, the user must program the VDD3P3V_PWDN register to power up the corresponding I/O buffers. For a list of multiplexed pins on the device and the pin mux group each pin belongs to, see Section 3.7.3.1, Multiplexed Pins on DM6431. 31 16 RESERVED R-0000 0000 0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RSV EMBK3 UR0FC UR0DAT TIMER1 TIMER0 SP PWM1 GPIO HOST EMBK2 EMBK1 EMBK0 CLKOUT R-00 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 3-1. VDD3P3V_PWDN Register— 0x01C4 0048 Table 3-2. VDD3P3V_PWDN Register Bit Descriptions(1) BIT NAME DESCRIPTION 31:14 RESERVED Reserved. Read-only, writes have no effect. Reserved. This bit should be programmed to 1 during device initialization (see Section 3.8, 13 RSV Device Initialization Sequence After Reset). EMIFA/VPSS Sub-Block 3 I/O Power Down Control. Controls the power of the 8 I/O pins in the EMIFA/VPSS Sub-Block 3. 12 EMBK3 0 = I/O pins powered up [default]. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z). UART0 Flow Control Block I/O Power Down Control. Controls the power of the 2 I/O pins in the UART0 Flow Control Block. 11 UR0FC 0 = I/O pins powered up. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default]. (1) For more details on I/O pins belonging to each pin mux block, see Section 3.7, Multiplexed Pin Configurations. Device Configurations 60 Submit Documentation Feedback |
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