TMS320DM6431 datasheet(83/227 Pages) TI1

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TMS320DM6431

Digital Media Processor

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SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

Table 3-18. PINMUX0 Register Description (continued)

Bit

Field Name

Description

Pins Controlled

8-bit EMIFA (Async) Pinout Mode 1 Address Width Select or Fast Boot PLL

Multiplier Select

This field serves two purposes:

If AEM = 001b, this field serves as the 8-bit EMIFA (Async) Pinout Mode 1

Address Width Select.

If FASTBOOT = 1 and AEM = 0 (000b) or 5 (101b), this field serves as the

Fastboot PLL Multiplier Select.

Fastboot PLL Multiplier Select: For more details on the AEAW pin functions as

Fastboot PLL Multiplier Select, see Section 3.4.1, Bootmodes.

EMIFA Address Width Select:

Sub-Block 0

000b = EMIFA (Async) pinout supports only EM_A[12:0] address pins.

EMIFA (Async) signals EM_A[20:13] are not pinned out. You get 6 GPIO pins

EM_A[13]/GP[51]

GP[51:46] and PINMUX bit field CI10SEL determines the function of the other

EM_A[14]/GP[50]

2 pins.

EM_A[15]/GP[49]

EM_A[16]/GP[48]

001b = EMIFA (Async) pinout supports only EM_A[14:0] address pins.

EM_A[17]/GP[47]

EMIFA (Async) signals EM_A[14:13] are pinned out.

18:16

AEAW(1)

EM_A[18]/GP[46]

EMIFA (Async) signals EM_A[20:15] are not pinned out. You get 4 GPIO pins

CI1(CCD9)/EM_A[19]/GP[45]

GP[49:46] and PINMUX0 bit field CI10SEL determines the function of the other

CI0(CCD8)/EM_A[20]/GP[44]

2 pins.

The combination of PINMUX0 fields AEM,

010b = EMIFA (Async) pinout supports only address pins EM_A[16:0].

AEAW, and CI10SEL control the muxing of

EMIFA (Async) signals EM_A[16:13] are pinned out.

these 8 pins. (2)

EMIFA (Async) signals EM_A[20:17] are not pinned out. You get 2 GPIO pins

GP[47:46] and PINMUX0 bit field CI10SEL determines the function of the other

2 pins.

011b = EMIFA (Async) pinout supports only address pins EM_A[18:0].

EMIFA (Async) signals EM_A[18:13] are pinned out.

EMIFA (Async) signals EM_A[20:19] are not pinned out. PINMUX0 bit field

CI10SEL determines the function of these 2 pins.

100b = EMIFA (Async) pinout supports address pins EM_A[20:0].

EMIFA (Async) signals EM_A[20:13] are pinned out. PINMUX0 bit field CI10SEL

must be programmed to 0.

101b through 111b = Reserved.

Reserved. For proper device operation, the user should only write "0" to these bits

15:12

RESERVED

(default).

Chip Select 3 Select.

Sub-Block 1

00 = GPIO pin (GP13) (default)

EM_CS3/GP[13]

11:10

CS3SEL

01 = EMIFA Chip Select 3 (EM_CS3)

The PINMUX0 field CS3SEL alone controls the

10 = Reserved

muxing of this pin.

11 = Reserved

Chip Select 4 Select.

Sub-Block 1

00 = GPIO pin (GP32) (default)

EM_CS4/GP[32]

9:8

CS4SEL

01 = EMIFA Chip Select 4 (EM_CS4)

The PINMUX0 field CS4SEL alone controls the

10 = Reserved

muxing of this pin.

11 = Reserved

Chip Select 5 Select.

Sub-Block 1

00 = GPIO pin (GP33) (default)

EM_CS5/GP[33]

7:6

CS5SEL

01 = EMIFA Chip Select 5 (EM_CS5)

The PINMUX0 field CS5SEL alone controls the

10 = Reserved

muxing of this pin.

11 = Reserved

Reserved. For proper device operation, the user should only write "0" to these bits

5:3

RESERVED

(default).

(1)

The AEAW default value is latched at reset from AEAW[2:0] configuration inputs. The latched values are also shown at

BOOTCFG.PLLMS (read-only).

(2)

For the full set of valid configurations of these pins, see Section 3.7.3.11.7, EMIFA/VPSS Block Pin-By-Pin Multiplexing Summary.

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