TMS320DM6431 datasheet(99/227 Pages) TI1

99 / 227 page

3.7.3.10 CLKOUT Block

3.7.3.11 EMIFA/VPSS Block Muxing

TMS320DM6431

Digital Media Processor

www.ti.com

SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

This block of 1 pin consists of CLKOUT, PWM2, and GPIO muxed pin (CLKOUT0/PWM2/GP[84]). The

PINMUX1.CKOBK register field selects the pin function in the CLKOUT Block.

Table 3-36 summarizes the 1 pin in the CLKOUT Block, its multiplexed function, and the PINMUX

configurations to select the corresponding function.

Table 3-36. CLKOUT Block Multiplexed Pin Selection

MULTIPLEXED FUNCTIONS

SIGNAL

CLKOUT0

PWM2

GPIO

NAME

FUNCTION

SELECT

FUNCTION

SELECT

FUNCTION

SELECT

CLKOUT0/

PWM2/

CLKOUT0

CKOBK = 01

PWM2

CKOBK = 10

GP[84]

CKOBK = 00

GP[84]

Table 3-37 provides a different view of the CLKOUT Block pin muxing, showing the CLKOUT Block

function based on PINMUX1.CKOBK setting. The selection options are also shown pictorially in

Figure 3-10.

Table 3-37. CLKOUT Block Function Selection

PINMUX1.CKOBK

BLOCK FUNCTION

RESULTING PIN FUNCTIONS

GPIO (1)

GPIO: GP[84]

CLKOUT (default)

Device Clock-Out: CLKOUT0

PWM2

PWM2: PWM2

Reserved

This block defaults to CLKOUT0 pin function.

In addition, the VDD3P3V_PWDN.CLKOUT field determines the power state of the CLKOUT Block pin.

The CLKOUT Block pin defaults to powered up. For more details on the VDD3P3V_PWDN.CLKOUT field,

see Section 3.2, Power Considerations.

This block of 61 pins consists of VPSS, EMIFA, and GPIO muxed pins. The following register fields affect

the pin functions in the EMIFA/VPSS Block:

• All PINMUX0 register fields: AEM, CS5SEL, CS4SEL, CS3SEL, AEAW, CCDCSEL, HVDSEL,

CWENSEL, CFLDSEL, and CI10SEL

The EMIFA/VPSS Block is divided into multiple sub-blocks for ultimate flexibility in pin multiplexing to

accommodate a wide variety of applications:

• Sub-Block 0: multiplexed between VPFE, EMIFA address/control pins, and GPIO.

• Sub-Block 1: multiplexed between EMIFA data/address/control pins, and GPIO.

• Sub-Block 2: no multiplexing. EMIFA control pins EM_WAIT/(RDY/BSY), EM_OE, EM_WE.

• Sub-Block 3: multiplexed between EMIFA address pins EM_A[12:6] and GPIO.

The EMBK0, EMBK1, EMBK2, EMBK3 fields in the VDD3P3V_PWDN register determine the power state

of the EMIFA/VPSS Block pins. The EMIFA/VPSS Block pins default to powered up. For more details on

the EMBK0, EMBK1, EMBK2, EMBK3 fields in the VDD3P3V_PWDN register, see Section 3.2, Power

Considerations.

To understand pin multiplexing in the EMIFA/VPSS Block, the user should start with Section 3.7.3.11.1,

EMIFA/VPSS Block Pin Selection Procedure, which outlines the procedures to select pin functions of this

block. Section 3.7.3.11.7, EMIFA/VPSS Block Pin-By-Pin Multiplexing Summary, provides a pin-by-pin

multiplexing summary for the EMIFA/VPSS Block. For more information on the PINMUX0 and PINMUX1

registers, see Section 3.7.2, Pin Muxing Selection After Device Reset.

Submit Documentation Feedback

Device Configurations

TMS320DM6431 Datasheet(PDF) 99 Page - Texas Instruments

TMS320DM6431 Datasheet(HTML) 99 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL