TMS320DM6431 datasheet(62/227 Pages) TI1

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3.3 Clock Considerations

3.3.1

Clock Configurations after Device Reset

3.3.1.1 Device Clock Frequency

3.3.1.2 Module Clock State

TMS320DM6431

Digital Media Processor

SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

Global device and local peripheral clocks are controlled by the PLL Controllers (PLLC1 and PLLC2) and

the Power and Sleep Controller (PSC). In addition, the System Module VPSS_CLKCTL register configures

the clock source to the Video Processing Subsystem (VPSS).

After device reset, the user is responsible for programming the PLL Controllers (PLLC1 and PLLC2) and

the Power and Sleep Controller (PSC) to bring the device up to the desired clock frequency and the

desired peripheral clock state (clock gating or not).

For additional power savings, some of the DM6431 peripherals support clock gating within the peripheral

boundary. For more details on clock gating and power saving features supported by a specific peripheral,

see the peripheral-specific reference guides [listed/linked in the TMS320DM643x DMP Peripherals

Overview Reference Guide (literature number SPRU983)].

The DM6431 defaults to PLL bypass mode. To bring the device up to the desired clock frequency, the

user should program PLLC1 and PLLC2 after device reset.

DM6431 supports a FASTBOOT option, where upon exit from device reset the internal bootloader code

automatically programs the PLLC1 into PLL mode with a specific PLL multiplier and divider to speed up

device boot. While the FASTBOOT option is beneficial for faster boot, the PLL multiplier and divider

selected for boot may not be the exact frequency desired for the run-time application. It is the user's

responsibility to reconfigure PLLC1 after fastboot to bring the device into the desired clock frequency.

Section 3.4.1, Boot Modes discusses the different fast boot modes in more detail.

The user must adhere to the various clock requirements when programming the PLLC1 and PLLC2:

• Fixed frequency ratio requirements between CLKDIV1, CLKDIV3, and CLKDIV6 clock domains. For

more details on the frequency ratio requirements, see Section 6.3.4, DM6431 Power and Clock

Domains.

• PLL multiplier and frequency ranges. For more details on PLL multiplier and frequency ranges, see

Section 6.7.1, PLL1 and PLL2.

The clock and reset state for each of the modules is controlled by the Power and Sleep Controller (PSC).

Table 3-3 shows the default state of each module after a device-level global reset. The DM6431 device

has four different module states—Enable, Disable, SyncReset, or SwRstDisable. For more information on

the definitions of the module states, the PSC, and PSC programming, see Section 6.3.5, Power and Sleep

Controller (PSC) and the TMS320DM643x DMP DSP Subsystem Reference Guide (literature number

SPRU978).

Table 3-3. DM6431 Default Module States

DEFAULT MODULE STATE

LPSC #

MODULE NAME

[PSC Register MDSTATn.STATE]

VPSS (Master)

SwRstDisable

VPSS (Slave)

SwRstDisable

EDMACC

SwRstDisable

EDMATC0

SwRstDisable

EDMATC1

SwRstDisable

EDMATC2

SwRstDisable

EMAC Memory Controller

SwRstDisable

MDIO

SwRstDisable

EMAC

SwRstDisable

McASP0

SwRstDisable

Device Configurations

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