TMS320DM6431 datasheet(80/227 Pages) TI1

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HostBlock(27pins)

(A)

GPIO(27)

HOSTBK=000

HOSTBK=100

EMAC(15)

MDIO

(2)

GPIO(10)

UART0DataBlock(2pins)

GPIO(2)

UR0DBK=0

UART

Data(2)

UR0DBK=1

UART0FlowControlBlock(2pins)

GPIO(2)

UR0FCBK=00

UART0

FlowCtrl(2)

UR0FCBK=01

PWM0(1)

UR0FCBK=10

GPIO(1)

Timer1Block(2pins)

GPIO(2)

TIM1BK=00

Timer1

(2)

TIM1BK=01

HECC

(2)

TIM1BK=11

Timer0Block(2pins)

(C)

GPIO(2)

TIM0BK=00

Timer0

(2)

TIM0BK=01

McBSP0

CLKS0(1)

TIM0BK=11

Timer0

TINPOL (1)

PWM1Block(1pin)

GPIO

(1)

PWM1BK=0

PWM1

(1)

PWM1BK=1

CLKOUTBlock(1pin)

GPIO

(1)

CKOBK=00

CLKOUT

(1)

CKOBK=01

PWM2

(1)

CKOBK=10

SerialPortSub-Block0(6pins)

(C)

GPIO(6)

SPBK0=00

McBSP0

(6)

SPBK0=01

McASP0Receive

and3Serializers(6)

SPBK0=10

SerialPortSub-Block1(6pins)

GPIO(6)

SPBK1=00

McASP0

Transmitand

1Serializer(6)

SPBK1=10

EMIFA/VPSSBlock(61pins)

(A)(B)

MajorConfig

Option A

8-10b

VPFE

GPIO

MajorConfig

OptionB

GPIO

8-10b

VPFE

8bEMIFA

(Async)

Pinout

Mode1

32KB-16MB

perCE

MajorConfig

OptionE

GPIO

8-10b

VPFE

8bEMIFA

(NAND)

Pinout

Mode5

AEM=000

AEM=001

AEM=101

TMS320DM6431

Digital Media Processor

SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

A high level view of the Pin Mux Blocks is shown in Figure 3-10. In each Pin Mux Block, the

PINMUX0/PINMUX1 default settings are underlined.

Note: Some default pin functions are determined by configuration pins (AEAW[2:0] and AEM[2:0]);

therefore, more than one configuration setting can serve as default based on the configuration pin settings

latched at device reset.

Default settings for PINMUX0 and PINMUX1 registers are underlined.

EMIFA/VPSS Block: shows the Major Config Options based on the AEM settings. Actual pin functions in the

EMIFA/VPSS Block are further determined by other PINMUX fields.

McBSP0 pins span multiple blocks (Serial Port Sub-Block0 and Timer0 Block). Serial Port Sub-Block0 contains most

of the pins needed for McBSP0 operation. Timer0 Block contains the optional external clock source input CLKS0.

Figure 3-10. Pin Mux Block Selection

Device Configurations

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TMS320DM6431 Datasheet(PDF) 80 Page - Texas Instruments

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