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TMS320DM6431 Datasheet(PDF) 85 Page - Texas Instruments |
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TMS320DM6431 Datasheet(HTML) 85 Page - Texas Instruments |
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85 / 227 page  3.7.2.2 PINMUX1 Register Description TMS320DM6431 Digital Media Processor www.ti.com SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008 The Pin Multiplexing 1 Register (PINMUX1) controls the pin multiplexing of all Pin Mux Blocks except the EMIFA/VPSS block. The PINMUX1 register format is shown in Figure 3-12 and the bit field descriptions are given in Table 3-19. Some muxed pins are controlled by more than one PINMUX bit field. For the combination of PINMUX bit fields that control each muxed pin, see Section 3.7.3.1, Multiplexed Pins on DM6431. 31 26 25 24 23 22 21 20 19 18 17 16 RESERVED SPBK1 SPBK0 TIM1BK RSV TIM0BK R/W-0000 00 R/W-00 R/W-00 R/W-00 R/W-00 R/W-00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM1B CKOBK RSV UR0FCBK RSV UR0DBK RSV HOSTBK RESERVED RSV K R/W-01 R/W-0 R/W-0 R/W-00 R/W-0 R/W-0 R/W-0 R/W-000 R/W-000 R-0 LEGEND: R/W = Read/Write; R = Read only; P = specified pin state; -n = value after reset (1) For proper DM6431 device operation, always write a value of "0" to all RESERVED/RSV bits. Figure 3-12. PINMUX1 Register— 0x01C4 0004 (1) Table 3-19. PINMUX1 Register Description Bit Field Name Description Pins Controlled Reserved. For proper device operation, the user should only write "0" to this bit 31:26 RESERVED – (default). Serial Port Sub-Block 1 Pin Select. Selects the function of the multiplexed pins in the Serial Port Sub-Block 1. Serial Port Sub-Block 1: 00 = GPIO Mode (default). AXR0[0]/GP[105] Pins function as GPIO (GP[110:105]). ACLKX0/GP[106] 25:24 SPBK1 01 = Reserved. AFSX0/GP[107] AHCLKX0/GP[108] 10 = McASP0 Transmit and 1 serializer. AMUTEIN0/GP[109] Pins function as McASP0: AXR0[0], ACLKX0, AFSX0, AHCLKX0, AMUTEIN0, AMUTE0/GP[110] and AMUTE0. 11 = Reserved. Serial Port Sub-Block 0 Pin Select. Selects the function of the multiplexed pins in the Serial Port Sub-Block 0. 00 = GPIO Mode (default). Serial Port Sub-Block 0: Pins function as GPIO (GP[104:99]). ACLKR0/CLKX0/GP[99] AFSR0/DR0/GP[100] 01 = McBSP0 Mode. 23:22 SPBK0 AHCLKR0/CLKR0/GP[101] Pins function as McBSP0 CLKX0, FSX0, DX0, CLKR0, FSR0, and DR0. AXR0[3]/FSR0/GP[102] AXR0[2]/FSX0/GP[103] 10 = McASP0 Receive and 3 serializers. AXR0[1]/DX0/GP[104] Pins function as McASP0 ACLKR0, AFSR0, AHCLKR0, AXR0_3, AXR0_2, and AXR0_1. 11 = Reserved Timer1 Block Pin Select. Selects the function of the multiplexed pins in theTimer1 Block. 00 = GPIO Mode (default). Pins function as GPIO (GP[56:55]). Timer1 Block: 21:20 TIM1BK 01 = Timer1 Mode. HECC_RX/TINP1L/GP[56] Pins function as Timer1 TINP1L and TOUT1L. HECC_TX/TOUT1L/GP[55] 10 = Reserved 11 = HECC Mode. Pins function as HECC HECC_RX and HECC_TX. Reserved. For proper device operation, the user should only write "0" to this bit 19:18 RSV – (default). Submit Documentation Feedback Device Configurations 85 |
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