TMS320DM6431 datasheet(101/227 Pages) TI1

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TMS320DM6431

Digital Media Processor

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SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

Table 3-38. EMIFA/VPSS Block Major Configuration Choices

PINMUX SELECTION

RESULTING PERIPHERALS/PINS

MAJOR

FIELDS(1)

CONFIG.

# GP PINS

VPFE AND # GP PINS

OPTION

AEM

CCDCSEL

EMIFA

(FROM GP[33:5])

(FROM GP[54:34])

# GP Pins

CCDCSEL

VPFE & # GP Pins

No CCDC

21 GP pins

000

0, 1

29 GP pins

8-to-10-bit CCDC

6-to-12 GP pins

No CCDC

8-bit EMIFA (ASYNC)

11-to-19 GP pins

Pinout Mode 1 with

001(2)

0, 1

9-to-13 GP pins

address pins to support

8-to-10-bit CCDC(2)

1(2)

32KB to 16MB per CS.

0-to-10 GP pins

No CCDC

21 GP pins

8-bit EMIFA (NAND)

101

0, 1

14-to-18 GP pins

Pinout Mode 5

8-to-10-bit CCDC

6-to-12 GP pins

(1)

For additional pin mux details for each Sub-Block, see Table 3-39 through Table 3-41, EMIFA/VPSS Sub-Block 0 Configuration Choices,

and Table 3-42 through Table 3-44, EMIFA/VPSS Sub-Block 1 Configuration Choices.

(2)

If PINMUX0.AEM = 001, it is not possible to get the C_WE pin for VPFE.

As shown in Table 3-38, the major configuration choices of the EMIFA/VPSS Block are determined by the

following PINMUX register fields:

• PINMUX0 register fields AEM and CCDCSEL

Based on the peripheral needs, select from the major configuration options in this block: Major

Configuration Options A, B, and E.

The following is an example on how to read Table 3-38. For example, the "PINMUX Selection Fields"

columns indicate that Major Configuration Choice B is selected through setting PINMUX0.AEM = 1 and

CCDCSEL = 0 or 1 (based on the system's VPFE requirement). The "Resulting Peripherals/Pins" columns

indicate that Major Configuration Option B can support the following combination of pin functions:

• Pins for 8-bit EMIFA (Async or NAND) function. The number of address pins supported provide

32KByte to 16MByte address reach per EMIFA Chip Select (CS) space.

• Pins for up to 10-bit VPFE. If 8-to-10-bit VPFE (CCDCSEL = 1) is selected, the user may have 0 to 10

GPIO pins. Exact detail on number of GPIO pins and VPFE control pins is furthered determined by

other PINMUX0 settings discussed in the EMIFA/VPSS Sub-Block 0 Configuration Choices.

• 9-to-13 GPIO pins from GP[33:5]. For details on the number of GPIO pins, see Section 3.7.3.11.4,

EMIFA/VPSS Sub-Block 1 Configuration Choices.

After using Table 3-38 to select the Major Configuration Option for the EMIFA/VPSS Block, proceed to

select the detailed pin choices in the EMIFA/VPSS Sub-Blocks.

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