PC87372 datasheet(143/144 Pages) NSC

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10.0 Device Characteristics (Continued)

143

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Revision 1.2

10.4.9 SWC Timing

Wake-Up Inputs at VSB3 Power Switching

Figure 47. Inputs at VSB3 Power Switching

Wake-Up Inputs at VDD3 Power Switching

Figure 48. Wake-Up Inputs at VDD3 Power Switching

Symbol

Figure

Description

Reference Conditions

Min

Max

tEWIV

External Wake-Up Inputs Valid1

1. Not tested. Guaranteed by characterization.

At VSB3 power on, after the

32 KHz Domain is toggling

24576 * tCP

2. tCP is the cycle time of the 32 KHz clock domain (see Low-Frequency Clock Timing on page 132)

32768 * tCP

Symbol

Figure

Description

Reference Conditions

Min

Max

tEWIV

External Wake-Up Inputs Valid1

1. Not tested. Guaranteed by characterization.

After VDD3 power on

2. The 32 KHz clock domain is assumed to be toggling at VDD3 power stable.

24576 * tCP

3. tCP is the cycle time of the 32 KHz clock domain (see Low-Frequency Clock Timing on page 132)

32768 * tCP

VSB3 (Power)

GPIOE13-10,

tEWIV

GPIO07-00,

KBCLK, MCLK

VSB3OFF

VSB3ON

KBDAT, MDAT

(Internal)

VSB Power-Up Reset

t32KW + t32KVAL

tIRST

32 KHz Domain

(Internal)

VDD3 (Power)

GPIOE13

-10,

tEWIV

GPIOE07-00

VDD3OFF

VDD3ON

(VDDLOAD = 1)

PC87372 Datasheet(PDF) 143 Page - National Semiconductor (TI)

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