11 / 58 page  CY7C66013 CY7C66113 Document #: 38-08024 Rev. *A Page 11 of 58 4.0 Product Summary Tables 4.1 Pin Assignments 4.2 I/O Register Summary I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads data from the selected port into the accumulator. IOWR performs the reverse; it writes data from the accumulator to the selected port. Indexed I/O Write (IOWX) adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Specifying address 0 (e.g., IOWX 0h) means the I/O register is selected solely by the contents of X. All undefined registers are reserved. It is important not to write to reserved registers as this may cause an undefined operation or increased current consumption during operation. When writing to registers with reserved bits, the reserved bits must be written with ‘0.’ Table 4-1. Pin Assignments Name I/O 48-Pin 56-Pin Description D+[0], D–[0] I/O 8, 9 8, 9 Upstream port, USB differential data. D+[1], D–[1] I/O 12, 13 13, 14 Downstream port 1, USB differential data. D+[2], D–[2] I/O 15, 16 16, 17 Downstream port 2, USB differential data. D+[3], D–[3] I/O 40, 41 48, 49 Downstream port 3, USB differential data. D+[4], D–[4] I/O 35, 36 44, 45 Downstream port 4, USB differential data. P0[7:0] I/O 21, 25, 22, 26, 23, 27, 24, 28 22, 32, 23, 33, 24, 34, 25, 35 GPIO Port 0. P1[7:0] I/O 6, 43, 5, 44, 4, 45, 47, 46 6, 51, 5, 52, 4, 53, 55, 54 GPIO Port 1. P2[7:0] I/O 19, 30, 18, 31, 17, 33, 14, 34 20, 38, 19, 39, 18, 41, 15, 42 GPIO Port 2. P3[6:0] I/O 37, 10, 39, 7, 42 43, 12, 46, 10, 47, 7, 50 GPIO Port 3, capable of sinking 12 mA (typical). DAC[7:0] I/O n/a 21, 29, 26, 30, 27, 31, 28, 37 Digital to Analog Converter (DAC) Port with programmable current sink outputs. DAC[1:0] offer a programmable range of 3.2 to 16 mA typical. DAC[7:2] have a programmable sink current range of 0.2 to 1.0 mA typical. XTALIN IN 2 2 6-MHz crystal or external clock input. XTALOUT OUT 1 1 6-MHz crystal out. VPP 29 36 Programming voltage supply, tie to ground during normal operation. VCC 48 56 Voltage supply. GND 11, 20, 32, 38 11, 40 Ground. VREF IN 3 3 External 3.3V supply voltage for the differential data output buffers and the D+ pull-up. Table 4-2. I/O Register Summary Register Name I/O Address Read/Write Function Page Port 0 Data 0x00 R/W GPIO Port 0 Data 20 Port 1 Data 0x01 R/W GPIO Port 1 Data 20 Port 2 Data 0x02 R/W GPIO Port 2 Data 20 Port 3 Data 0x03 R/W GPIO Port 3 Data 20 Port 0 Interrupt Enable 0x04 W Interrupt Enable for Pins in Port 0 21 Port 1 Interrupt Enable 0x05 W Interrupt Enable for Pins in Port 1 22 Port 2 Interrupt Enable 0x06 W Interrupt Enable for Pins in Port 2 22 Port 3 Interrupt Enable 0x07 W Interrupt Enable for Pins in Port 3 22 GPIO Configuration 0x08 R/W GPIO Port Configurations 20 |
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