CY7C66013
CY7C66113
Document #: 38-08024 Rev. *A
Page 31 of 58
Although Reset is not an interrupt, the first instruction executed after a reset is at PROM address 0x0000h—which corresponds
to the first entry in the Interrupt Vector Table. Because the JMP instruction is two bytes long, the interrupt vectors occupy two bytes.
16.2
Interrupt Latency
Interrupt latency can be calculated from the following equation:
Interrupt latency =
(Number of clock cycles remaining in the current instruction) + (10 clock cycles for the CALL instruction) +
(5 clock cycles for the JMP instruction).
For example, if a five-clock cycle instruction such as JC is being executed when an interrupt occurs, the first instruction of the
Interrupt Service Routine executes a minimum of 16 clocks (1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt is
issued. For a 12-MHz internal clock (6-MHz crystal), 20 clock periods is 20/12 MHz = 1.667
µs.
16.3
USB Bus Reset Interrupt
The USB Controller recognizes a USB Reset when a Single Ended Zero (SE0) condition persists on the upstream USB port for
12–16
µs. SE0 is defined as the condition in which both the D+ line and the D– line are LOW. A USB Bus Reset may be recognized
for an SE0 as short as 12
µs, but is always recognized for an SE0 longer than 16 µs. When a USB Bus Reset is detected, bit 5
of the Processor Status and Control Register (Figure 15-1) is set to record this event. In addition, the controller clears the following
registers:
SIE Section:
USB Device Address Registers (0x10, 0x40)
Hub Section:
Hub Ports Connect Status (0x48)
Hub Ports Enable (0x49)
Hub Ports Speed (0x4A)
Hub Ports Suspend (0x4D)
Hub Ports Resume Status (0x4E)
Hub Ports SE0 Status (0x4F)
Hub Ports Data (0x50)
Hub Downstream Force (0x51).
A USB Bus Reset Interrupt is generated at the end of the USB Bus Reset condition when the SE0 state is deasserted. If the USB
reset occurs during the start-up delay following a POR, the delay is aborted as described in Section 7.1.
16.4
Timer Interrupt
There are two periodic timer interrupts: the 128-
µs interrupt and the 1.024-ms interrupt. The user should disable both timer
interrupts before going into the suspend mode to avoid possible conflicts between servicing the timer interrupts first or the suspend
request first.
Table 16-1. Interrupt Vector Assignments
Interrupt Vector Number
ROM Address
Function
Not Applicable
0x0000
Execution after Reset begins here
1
0x0002
USB Bus Reset interrupt
2
0x0004
128-
µs timer interrupt
3
0x0006
1.024-ms timer interrupt
4
0x0008
USB Address A Endpoint 0 interrupt
5
0x000A
USB Address A Endpoint 1 interrupt
6
0x000C
USB Address A Endpoint 2 interrupt
7
0x000E
USB Address B Endpoint 0 interrupt
8
0x0010
USB Address B Endpoint 1 interrupt
9
0x0012
USB Hub interrupt
10
0x0014
DAC interrupt
11
0x0016
GPIO interrupt
12
0x0018
I2C interrupt
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