CY7C66013
CY7C66113
Document #: 38-08024 Rev. *A
Page 22 of 58
Port 1 Interrupt Enable
ADDRESS 0x05
Port 2 Interrupt Enable
ADDRESS 0x06
Port 3 Interrupt Enable
ADDRESS 0x07
10.0
DAC Port
The CY7C66113 features a programmable sink current 8 bit port which is also known as DAC port. Each of these port I/O pins
have a programmable current sink. Writing a ‘1’ to a DAC I/O pin disables the output current sink (Isink DAC) and drives the I/O
pin HIGH through an integrated 14-k
Ω resistor. When a ‘0’ is written to a DAC I/O pin, the I
sink DAC is enabled and the pull-up
resistor is disabled. This causes the Isink DAC to sink current to drive the output LOW. Figure 10-1 shows a block diagram of the
DAC port pin.
The amount of sink current for the DAC I/O pin is programmable over 16 values based on the contents of the DAC Isink Register
(Figure 10-3) for that output pin. DAC[1:0] are high current outputs that are programmable from 3.2 mA to 16 mA (typical).
DAC[7:2] are low current outputs, programmable from 0.2 mA to 1.0 mA (typical).
When the suspend bit in Processor Status and Control Register (Figure 15-1) is set, the Isink DAC block of the DAC circuitry is
disabled. Special care should be taken when the CY7C66113 device is placed in the suspend. The DAC Port Data
Register(Figure 10-2) should normally be loaded with all ‘1’s (Figure 15-1) before setting the suspend bit. If any of the DAC bits
Bit #
7
65
43
210
Bit Name
P1.7 Intr
Enable
P1.6 Intr
Enable
P1.5 Intr
Enable
P1.4 Intr
Enable
Reserved
P0.2 Intr
Enable
P1.1 Intr
Enable
P1.0 Intr
Enable
Read/Write
WWW
W
W
WWW
Reset
0
00
00
000
Figure 9-8. Port 1 Interrupt Enable
Bit #
7
65
43
210
Bit Name
P0.7 Intr
Enable
P0.6 Intr
Enable
P0.5 Intr
Enable
P0.4 Intr
Enable
P0.3 Intr
Enable
Reserved
Reserved
Reserved
Read/Write
WWW
W
W
WWW
Reset
0
00
00
000
Figure 9-9. Port 2 Interrupt Enable
Bit #
7
65
43
210
Bit Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
P3.1 Intr
Enable
P0.3 Intr
Enable
Read/Write
WWW
W
W
WWW
Reset
0
00
00
000
Figure 9-10. Port 3 Interrupt Enable
Figure 10-1. Block Diagram of a DAC Pin
VCC
14 k
Ω
Data
Out
Latch
Internal
Data Bus
DAC Read
DAC Write
Interrupt
Enable
to Interrupt
Controller
Q1
Internal
Buffer
Interrupt
Polarity
Isink
DAC
Isink
Register
4 bits
DAC
I/O Pin
Suspend
(Bit 3 of Register 0xFF)
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