CY7C66013
CY7C66113
Document #: 38-08024 Rev. *A
Page 27 of 58
This bit is set by the I2C-compatible block during the first byte of a slave receive transaction, after an I2C start or restart.
The Addr bit is cleared when the firmware sets the Continue bit. This bit allows the firmware to recognize when the master
has lost arbitration, and in slave mode it allows the firmware to recognize that a start or restart has occurred.
Bit 2 : ARB Lost/Restart
This bit is valid as a status bit (ARB Lost) after master mode transactions. In master mode, set this bit (along with the
Continue and MSTR Mode bits) to perform an I2C restart sequence. The I2C target address for the restart must be written
to the data register before setting the Continue bit. To prevent false ARB Lost signals, the Restart bit is cleared by hardware
during the restart sequence.
Bit 1 : Receive Stop
This bit is set when the slave is in receive mode and detects a stop bit on the bus. The Receive Stop bit is not set if the
firmware terminates the I2C transaction by not acknowledging the previous byte transmitted on the I2C-compatible bus,
e.g. in receive mode if firmware sets the Continue bit and clears the ACK bit.
Bit 0 : I2C Enable
Set this bit to override GPIO definition with I2C-compatible function on the two I2C-compatible pins. When this bit is cleared,
these pins are free to function as GPIOs. In I2C-compatible mode, the two pins operate in open drain mode, independent
of the GPIO configuration setting.
14.0
Hardware Assisted Parallel Interface (HAPI)
The CY7C66x13 processor provides a hardware assisted parallel interface for bus widths of 8, 16, or 24 bits, to accommodate
data transfer with an external microcontroller or similar device. Control bits for selecting the byte width are in the HAPI/I2C
Configuration Register (Figure 12-1), bits 1 and 0.
Signals are provided on Port 2 to control the HAPI interface. Table 14-1 describes these signals and the HAPI control bits in the
HAPI/I2C Configuration Register. Enabling HAPI causes the GPIO setting in the GPIO Configuration Register (Figure 9-6) to be
overridden. The Port 2 output pins are in CMOS output mode and Port 2 input pins are in input mode (open drain mode with Q3
OFF in Figure 9-1).
HAPI Read by External Device from CY7C66x13:
In this case (see Figure 25-3), firmware writes data to the GPIO ports. If 16-bit or 24-bit transfers are being made, Port 0 should
be written last, since writes to Port 0 asserts the Data Ready bit and the DReadyPin to signal the external device that data is
available.
The external device then drives the OE and CS pins active (LOW), which causes the HAPI data to be output on the port pins.
When OE is returned HIGH (inactive), the HAPI/GPIO interrupt is generated. At that point, firmware can reload the HAPI latches
for the next output, again writing Port 0 last.
The Data Ready bit reads the opposite state from the external DReadyPin on pin P2[3]. If the DRDY Polarity bit is 0, DReadyPin
is active HIGH, and the Data Ready bit is active LOW.
HAPI Write by External Device to CY7C66x13:
Table 14-1. Port 2 Pin and HAPI Configuration Bit Definitions
Pin
Name
Direction
Description (Port 2 Pin)
P2[2]
LatEmptyPin
Out
Ready for more input data from external interface.
P2[3]
DReadyPin
Out
Output data ready for external interface.
P2[4]
STB
In
Strobe signal for latching incoming data.
P2[5]
OE
In
Output Enable, causes chip to output data.
P2[6]
CS
In
Chip Select (Gates STB and OE).
Bit
Name
R/W
Description (HAPI/I2C Configuration Register)
2
Data Ready
R
Asserted after firmware writes data to Port 0, until OE driven LOW.
3
Latch Empty
R
Asserted after firmware reads data from Port 0, until STB driven LOW.
4
DRDY Polarity
R/W
Determines polarity of Data Ready bit and DReadyPin:
If 0, Data Ready is active LOW, DReadyPin is active HIGH.
If 1, Data Ready is active HIGH, DReadyPin is active LOW.
5
LEMPTY Polarity
R/W
Determines polarity of Latch Empty bit and LatEmptyPin:
If 0, Latch Empty is active LOW, LatEmptyPin is active HIGH.
If 1, Latch Empty is active HIGH, LatEmptyPin is active LOW.
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