CY7C66013
CY7C66113
Document #: 38-08024 Rev. *A
Page 19 of 58
It is possible for the WDR bit of the Processor Status and Control Register (0xFF) to be set following a POR event. If a firmware
interrogates the Processor Status and Control Register for a set condition on the WDR bit, the WDR bit should be ignored if the
POR (bit 3 of register 0xFF) bit is set.
8.0
Suspend Mode
The CY7C66x13 can be placed into a low-power state by setting the Suspend bit of the Processor Status and Control register.
All logic blocks in the device are turned off except the GPIO interrupt logic and the USB receiver. The clock oscillator and PLL,
as well as the free-running and WDTs, are shut down. Only the occurrence of an enabled GPIO interrupt or non-idle bus activity
at a USB upstream or downstream port wakes the part from suspend. The Run bit in the Processor Status and Control Register
must be set to resume a part out of suspend.
The clock oscillator restarts immediately after exiting suspend mode. The microcontroller returns to a fully functional state 1 ms
after the oscillator is stable. The microcontroller executes the instruction following the I/O write that placed the device into suspend
mode before servicing any interrupt requests.
The GPIO interrupt allows the controller to wake-up periodically and poll system components while maintaining a very low average
power consumption. To achieve the lowest possible current during suspend mode, all I/O should be held at VCC or Gnd. This also
applies to internal port pins that may not be bonded in a particular package.
Typical code for entering suspend is shown below:
...
; All GPIO set to low-power state (no floating pins)
...
; Enable GPIO interrupts if desired for wake-up
mov a, 09h
; Set suspend and run bits
iowr FFh
; Write to Status and Control Register – Enter suspend, wait for USB activity (or GPIO Interrupt)
nop
; This executes before any ISR
...
; Remaining code for exiting suspend routine.
9.0
General-purpose I/O (GPIO) Ports
Figure 9-1. Block Diagram of a GPIO Pin
GPIO
VCC
14 k
Ω
GPIO
CFG
mode
2-bits
Data
Out
Latch
Internal
Data Bus
Port Read
Port Write
Interrupt
Enable
Interrupt
Controller
Q1
Q3*
Q2
*Port 0,1,2: Low Isink
Port 3: High Isink
Data
Interrupt
Latch
OE
Reg_Bit
STRB
Data
In
Latch
(Latch is Transparent
except in HAPI mode)
PIN
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