CY7C66013
CY7C66113
Document #: 38-08024 Rev. *A
Page 20 of 58
There are up to 31 GPIO pins (P0[7:0], P1[7:0], P2[7:0], and P3[6:0]) for the hardware interface. The number of GPIO pins
changes based on the package type of the chip. Each port can be configured as inputs with internal pull-ups, open drain outputs,
or traditional CMOS outputs. Port 3 offers a higher current drive, with typical current sink capability of 12 mA. The data for each
GPIO port is accessible through the data registers. Port data registers are shown in Figure 9-2 through Figure 9-5, and are set
to 1 on reset.
Port 0 Data
ADDRESS 0x00
Port 1 Data
ADDRESS 0x01
Port 2 Data
ADDRESS 0x02
Port 3 Data
ADDRESS 0x03
Special care should be taken with any unused GPIO data bits. An unused GPIO data bit, either a pin on the chip or a port bit that
is not bonded on a particular package, must not be left floating when the device enters the suspend state. If a GPIO data bit is
left floating, the leakage current caused by the floating bit may violate the suspend current limitation specified by the USB
specifications. If a ‘1’ is written to the unused data bit and the port is configured with open drain outputs, the unused data bit
remains in an indeterminate state. Therefore, if an unused port bit is programmed in open-drain mode, it must be written with a
‘0.’ Notice that the CY7C66013 always requires that P3[7:5] be written with a ‘0.’ When the CY7C66113 is used the P3[7] should
be written with a ‘0.’
In normal non-HAPI mode, reads from a GPIO port always return the present state of the voltage at the pin, independent of the
settings in the Port Data Registers. If HAPI mode is activated for a port, reads of that port return latched data as controlled by the
HAPI signals (see Section 14.0). During reset, all of the GPIO pins are set to a high impedance input state (‘1’ in open drain
mode). Writing a ‘0’ to a GPIO pin drives the pin LOW. In this state, a ‘0’ is always read on that GPIO pin unless an external source
overdrives the internal pull-down device.
9.1
GPIO Configuration Port
Every GPIO port can be programmed as inputs with internal pull-ups, outputs LOW or HIGH, or Hi-Z (floating, the pin is not driven
internally). In addition, the interrupt polarity for each port can be programmed. The Port Configuration bits (Figure 9-6) and the
Interrupt Enable bit (Figure 9-7 through Figure 9-10) determine the interrupt polarity of the port pins.
GPIO Configuration
ADDRESS 0x08
Bit #
7
65
43
210
Bit Name
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
11
11
111
Figure 9-2. Port 0 Data
Bit #
7
65
43
210
Bit Name
P1.7
P1.6
P1.5
P1.4
Reserved
P1.2
P1.1
P1.0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
11
11
111
Figure 9-3. Port1 Data
Bit #
7
65
43
210
Bit Name
P2.7
P2.6
P2.5
P2.4
P2.3
Reserved
Reserved
Reserved
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
11
11
111
Figure 9-4. Port 2 Data
Bit #
7
65
43
210
Bit Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
P3.1
P3.0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
11
11
111
Figure 9-5. Port 3 Data
Bit #
7
65
43
210
Bit Name
Port 3
Config Bit 1
Port 3
Config Bit 0
Port 2
Config Bit 1
Port 2
Config Bit 0
Port 1
Config Bit 1
Port 1
Config Bit 0
Port 0
Config Bit 1
Port 0
Config Bit 0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
00
00
000
Figure 9-6. GPIO Configuration Register
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