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AD9689-2000EBZ Datasheet(PDF) 118 Page - Analog Devices

Part # AD9689-2000EBZ
Description  Dual Analog-to-Digital Converter
PDF  134 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9689-2000EBZ Datasheet(HTML) 118 Page - Analog Devices

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AD9689
Data Sheet
Rev. A | Page 118 of 134
Addr.
Name
Bit(s) Bit Name
Setting
Description
Reset
Access
[3:0] Test mode selection
Test mode generation selection.
0x0
R/W
0000
Off (normal operation).
0001
Midscale short.
0010
Positive full scale.
0011
Negative full scale.
0100
Alternating checker board.
0101
PN sequence (long).
0110
PN sequence (short).
0111
1/0 word toggle.
1000
User pattern test mode (used with Register 0x0550, Bit 7 and the User
Pattern 1, User Pattern 2, User Pattern 3, and User Pattern 4 registers).
1111
Ramp output.
0x0551 User Pattern 1
LSB
[7:0] User Pattern 1[7:0]
User Test Pattern 1 least significant byte.
0x0
R/W
0x0552 User Pattern 1
MSB
[7:0] User Pattern 1[15:8]
User Test Pattern 1 least significant byte.
0x0
R/W
0x0553 User Pattern 2
LSB
[7:0] User Pattern 2[7:0]
User Test Pattern 2 least significant byte.
0x0
R/W
0x0554 User Pattern 2
MSB
[7:0] User Pattern 2[15:8]
User Test Pattern 2 least significant byte.
0x0
R/W
0x0555 User Pattern 3
LSB
[7:0] User Pattern 3[7:0]
User Test Pattern 3 least significant byte.
0x0
R/W
0x0556 User Pattern 3
MSB
[7:0] User Pattern 3[15:8]
User Test Pattern 3 least significant byte.
0x0
R/W
0x0557 User Pattern 4
LSB
[7:0] User Pattern 4[7:0]
User Test Pattern 4 least significant byte.
0x0
R/W
0x0558 User Pattern 4
MSB
[7:0] User Pattern 4[15:8]
User Test Pattern 4 least significant byte.
0x0
R/W
0x0559 Output Mode
Control 1
[7:4] Converter control
Bit 1 selection
0x0
R/W
0000
Tie low (1'b0).
0001
Overrange bit.
0010
Signal monitor bit.
0011
Fast detect (FD) bit.
0101
SYSREF.
[3:0] Converter control
Bit 0 selection
0x0
R/W
0000
Tie low (1'b0).
0001
Overrange bit.
0010
Signal monitor bit.
0011
Fast detect (FD) bit.
0101
SYSREF.
0x055A Output Mode
Control 2
[7:4] Reserved
Reserved.
0x0
R
[3:0] Converter control
Bit 2 selection
0x1
R/W
0000
Tie low (1'b0).
0001
Overrange bit.
0010
Signal monitor bit.
0011
Fast detect (FD) bit.
0101
SYSREF.
0x0561 Out sample
mode
[7:3] Reserved
Reserved.
0x0
R/W
2
Sample invert
0x0
R/W
0
ADC sample data is not inverted.
1
ADC sample data is inverted.
[1:0] Data format select
0x1
R/W
00
Offset binary.
01
Twos complement (default).
0x0562 Out overrange
clear
[7:0] Data format
overrange clear
Overrange clear bits (one bit for each virtual converter). Writing a 1 to the
overrange clear bit clears the corresponding overrange sticky bit.
0x0
R/W
0
Overrange bit enabled.
1
Overrange bit cleared.



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