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AD9925BBCZ Datasheet(PDF) 58 Page - Analog Devices

Part # AD9925BBCZ
Description  CCD Signal Processor with Vertical Driver and Precision Timing Generator
PDF  96 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9925BBCZ Datasheet(HTML) 58 Page - Analog Devices

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AD9925
Rev. A | Page 58 of 96
SUBCK
VL
VH2
RSTB
NC
SL
L9
J7
J8
K8
K9
L10
L11
K11
REFB
MSHUT
CLI
AVSS
AVSS
CCDIN
AVDD
REFT
J6
K6
L7
L6
K7
L8
D0 (LSB)
VSUB
VDVDD
TCVDD
TCVDD
CLO
SYNC
D9925
TO SCALE
K3
K4
J4
J5
K5
L5
A1
B2
A3
TCVSS
TCVSS
A4
A5
D11
E10
DCLK
NC
NC
A2
NC
NC
NC
B3
D9
D8
D7
D6
D5
D4
D3
D2
D11 (MSB)
D10
D1
DRVSS
DRVDD
A
NOT DRAWN
A7
B7
A8
A9
A10
B11
B10
C11
B5
C5
A6
B6
C10
NC
VDVSS
C4
B4
RGVSS
L2
L3
RGVSS
K2
RG
RGVDD
L4
ANALOG OUTPUT
FROM CCD
+3V ANALOG
SUPPLY
+3V H, RG SUPPLY
MASTER CLOCK INPUT
+
12
ATA
UTS
D
OUTP
+3V DRIVER
+
DCLK TO ASIC/DSP
3
SERIAL INTERFACE
(FROM ASIC/DSP)
VSUB TO CCD
EXTERNAL SYNC INPUT
H1 TO H4, RG OUTPUTS
(TO CCD)
+3V H, RG SUPPLY
+
TO STROBE CIRCUIT
TO SHUTTER CIRCUIT
–7.5V SUPPLY
+15V SUPPLY
+3V ANALOG SUPPLY
SUBCK OUTPUT TO CCD
–7.5V SUPPLY
+15V SUPPLY
VERTICAL CLOCK OUTPUTS
(TO CCD)
10
HORIZONTAL SYNC TO/FROM ASIC/DSP
VERTICAL SYNC TO/FROM ASIC/DSP
EXTERNAL RESET INPUT
(NORMALLY HIGH,
PULSE LOW TO RESET)
3
+3V ANALOG SUPPLY
0.1
µF
4.7
µF
0.1
µF
0.1
µF
4.7
µF
Figure 73. AD9925 Typical Circuit Configuration
0.1
µF
4.7
µF
0.1
µF
0.1
µF
1
µF
1
µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF



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