=

£

p ´

´

SW

0

OUT

f

1

f

2

ESR

C

3

9

+

8

PWM

VDDQSNS

REFIN

6

VREF

Control

Logic

and

Driver

R1

R2

14

11

DRVH

DRVL

+

1.8 V

V

IN

Lx

ESR

C

OUT

R

LOAD

UDG-10136

High-Side

MOSFET

Low-Side

MOSFET

VDDQ

TPS51216

www.ti.com

SLUSAB9A – NOVEMBER 2010 – REVISED APRIL 2013

D-CAP™ Mode

Figure 30 shows a simplified model of D-CAP™ mode architecture.

Figure 30. Simplified D-CAP™ Model

The VDDQSNS voltage is compared with REFIN voltage. The PWM comparator creates a set signal to turn on

the high-side MOSFET. The gain and speed of the comparator is high enough to maintain the voltage at the

beginning of each on-cycle (or the end of each off-cycle) to be substantially constant. The DC output voltage

monitored at VDDQ may have line regulation due to ripple amplitude that slightly increases as the input voltage

increase. The D-CAP™ mode offers flexibility on output inductance and capacitance selections and provides

ease-of-use with a low external component count. However, it requires a sufficient amount of output ripple

voltage for stable operation and good jitter performance.

The requirement for loop stability is simple and is described in Equation 1. The 0-dB frequency, f0 defined in

Equation 1, is recommended to be lower than 1/3 of the switching frequency to secure proper phase margin.

where

•

ESR is the effective series resistance of the output capacitor

•

COUT is the capacitance of the output capacitor

•

fsw is switching frequency

(1)

Jitter is another attribute caused by signal-to-noise ratio of the feedback signal. One of the major factors that

determine jitter performance in D-CAP™ mode is the down-slope angle of the VDDQSNS ripple voltage.

Figure 31 shows, in the same noise condition, a jitter is improved by making the slope angle larger.

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