12

17

16

6

15

14

13

11

V5IN

TPS51216

S3

S5

VREF

VBST

DRVH

SW

DRVL

8

10

REFIN

PGND

7

19

GND

MODE

18 TRIP

20

9

2

3

PGOOD

VDDQSNS

VLDOIN

VTT

1

4

5

VTTSNS

VTTGND

VTTREF

UDG-13089

VDDQ

S5

PGND

5VIN

PGND

VIN

AGND

Powergood

PGND

1 kW

PGND

PGND

0.22 mF

AGND

TPS51216

www.ti.com

SLUSAB9A – NOVEMBER 2010 – REVISED APRIL 2013

VTT and VTTREF

TPS51216 integrates two high performance, low-drop-out linear regulators, VTT and VTTREF, to provide

complete DDR2/DDR3/DDR3L power solutions. The VTTREF has a 10-mA sink/source current capability, and

tracks ½ of VDDQSNS with ±1% accuracy using an on-chip ½ divider. A 0.22-

μF (or larger) ceramic capacitor

must be connected close to the VTTREF terminal for stable operation. The VTT responds quickly to track

VTTREF within ±40 mV at all conditions, and the current capability is 2 A for both sink and source. A 10-

μF (or

larger) ceramic capacitor(s) need to be connected close to the VTT terminal for stable operation. To achieve tight

regulation with minimum effect of wiring resistance, a remote sensing terminal, VTTSNS, should be connected to

the positive node of VTT output capacitor(s) as a separate trace from the high-current line to the VTT pin.

(Please refer to the Layout Considerations section for details.)

When VTT is not required in the design, the following treatments are strongly recommended.

•

Connect VLDOIN to VDDQ.

•

Tie VTTSNS to VTT, and remove capacitors from VTT to float.

•

Connect VTTGND to GND.

•

Select MODE 0 or MODE 1 shown in Table 2 (Select Non-tracking discharge mode).

•

Maintain a 0.22-µF capacitor connected at VTTREF.

•

Pull-down S3 to GND with 1-k

Ω resistance.

Figure 32. Application Circuit When VTT Is Not Required

Copyright © 2010–2013, Texas Instruments Incorporated

Submit Documentation Feedback

19

Product Folder Links :TPS51216