DA9213 datasheet(31/62 Pages) DIALOG

31 / 62 page

DA9213, DA9214, and DA9215

Multi-Phase 5A/Phase DC-DC Buck Converter

Datasheet

Revision 2.2

23-Oct-2017

CFR0011-120-00

31 of 62

active page, it is recommended to read back the page control register to ensure that future data

exchange is accessing the intended registers.

All registers outside the DA9213, DA9214, and DA9215 range are write only, that is, the DA9213,

DA9214, and DA9215 will not answer to a read command and the data bus is tristate (they are

implicitly directed to DA9063). In particular the information contained in registers 0x105 and 0x106 is

used by DA9213, DA9214, and DA9215 to configure the control interface. They must be the same as

the main PMIC (DA9063), so that a write to those registers configures both the main PMIC and

DA9213, DA9214, and DA9215 at the same time. The default OTP settings also need to be identical

for a correct operation of the system.

The 4-WIRE interface features a half-duplex operation, that is, data can be transmitted and received

within a single 16-bit frame at enhanced clock speed (up to 14 MHz). It operates at the clock

frequencies provided by the host.

Figure 19: Schematic of 4-WIRE and 2-WIRE Power Manager Bus

A transmission begins when initiated by the host. Reading and writing is accomplished by the use of

an 8-bit command, which is sent by the host prior to the exchanged 8-bit data. The byte from the host

begins shifting in on the SI pin under the control of the serial clock SK provided from the host. The

first seven bits specify the register address (0x01 to 0x07) that will be written or read by the host. The

word ends with an R/W bit, which together with the control bit R/W_POL specifies the direction of the

following data exchange. During register writing the host continues sending out data during the

following eight SK clocks. For reading, the host stops transmitting and the 8-bit register is clocked out

of DA9213, DA9214, and DA9215 during the consecutive eight SK clocks of the frame. Address and

data are transmitted with MSB first. The polarity (active state) of nCS is defined by control bit

nCS_POL. nCS resets the interface when inactive and it has to be released between successive

cycles.

The SO output from DA9213, DA9214, and DA9215 is normally in high-impedance state and active

only during the second half of read cycles. A pull-up or pull-down resistor may be needed at the SO

line if a floating logic signal can cause unintended current consumption inside other circuits.

Table 10: 4-WIRE Clock Configurations

CPHA Clock

Polarity

CPOL Clock

Phase

Output Data is Updated at SK

Edge

Input Data is Registered at SK

Edge

0 (idle low)

Falling

Rising

0 (idle low)

Rising

Falling

1 (idle high)

Rising

Falling

1 (idle high)

Falling

Rising

PMIC

(slave)

Host

processor

nCS/nSS

VDDIO

Slave device

nCS/nSS

VDDIO

4-WIRE interface

Host

processor

PMIC

Peripheral

device

Peripheral

device

SDA

SCL

SDA

VDDIO

2-WIRE interface

DA9213 Datasheet(PDF) 31 Page - Dialog Semiconductor

DA9213 Datasheet(HTML) 31 Page - Dialog Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Datasheet Download

Link URL