TMS320VC5503 datasheet(81/123 Pages) TI

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Electrical Specifications

April 2004 − Revised January 2005

SPRS245C

5.7.2 Synchronous DRAM (SDRAM) Timings

Table 5−9 and Table 5−10 assume testing over recommended operating conditions (see Figure 5−8 through

Figure 5−14).

Table 5−9. Synchronous DRAM Cycle Timing Requirements

NO.

CVDD = 1.2 V

CVDD = 1.35 V

CVDD = 1.6 V

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

M19

tsu(DV-CLKMEMH)

Setup time, read data valid before CLKMEM high

M20

th(CLKMEMH-DV)

Hold time, read data valid after CLKMEM high

M21

tc(CLKMEM)

Cycle time, CLKMEM

9.26†

7.52‡

† Maximum SDRAM operating frequency = 108 MHz. Actual attainable maximum operating frequency will depend on the quality of the PC board

design and the memory chip timing requirement.

‡ Maximum SDRAM operating frequency = 133 MHz. Actual attainable maximum operating frequency will depend on the quality of the PC board

design and the memory chip timing requirement.

Table 5−10. Synchronous DRAM Cycle Switching Characteristics

NO.

PARAMETER

CVDD = 1.2 V

CVDD = 1.35 V

CVDD = 1.6 V

UNIT

NO.

PARAMETER

MIN

MAX

MIN

MAX

UNIT

M22

td(CLKMEMH-CEL)

Delay time, CLKMEM high to CEx low

1.2

M23

td(CLKMEMH-CEH)

Delay time, CLKMEM high to CEx high

1.2

M24

td(CLKMEMH-BEV)

Delay time, CLKMEM high to BEx valid

1.2

M25

td(CLKMEMH-BEIV)

Delay time, CLKMEM high to BEx invalid

1.2

M26

td(CLKMEMH-AV)

Delay time, CLKMEM high to address valid

1.2

M27

td(CLKMEMH-AIV)

Delay time, CLKMEM high to address invalid

1.2

M28

td(CLKMEMH-SDCASL)

Delay time, CLKMEM high to SDCAS low

1.2

M29

td(CLKMEMH-SDCASH)

Delay time, CLKMEM high to SDCAS high

1.2

M30

td(CLKMEMH-DV)

Delay time, CLKMEM high to data valid

1.2

M31

td(CLKMEMH-DIV)

Delay time, CLKMEM high to data invalid

1.2

M32

td(CLKMEMH-SDWEL)

Delay time, CLKMEM high to SDWE low

1.2

M33

td(CLKMEMH-SDWEH)

Delay time, CLKMEM high to SDWE high

1.2

M34

td(CLKMEMH-SDA10V)

Delay time, CLKMEM high to SDA10 valid

1.2

M35

td(CLKMEMH-SDA10IV)

Delay time, CLKMEM high to SDA10 invalid

1.2

M36

td(CLKMEMH-SDRASL)

Delay time, CLKMEM high to SDRAS low

1.2

M37

td(CLKMEMH-SDRASH)

Delay time, CLKMEM high to SDRAS high

1.2

M38

td(CLKMEMH–CKEL)

Delay time, CLKMEM high to CKE low

1.2

M39

td(CLKMEMH–CKEH)

Delay time, CLKMEM high to CKE high

1.2

TMS320VC5503 Datasheet(PDF) 81 Page - Texas Instruments

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