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TMS320VC5503 Datasheet(PDF) 97 Page - Texas Instruments |
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TMS320VC5503 Datasheet(HTML) 97 Page - Texas Instruments |
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97 / 123 page  Electrical Specifications 97 April 2004 − Revised January 2005 SPRS245C Table 5−24. McBSP0 Switching Characteristics†‡ NO. PARAMETER CVDD = 1.2 V CVDD = 1.35 V CVDD = 1.6 V UNIT NO. PARAMETER MIN MAX MIN MAX UNIT MC1 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P 2P ns MC3 tr(CKRX) Rise time, CLKR/X CLKR/X int 1 1 ns MC4 tf(CKRX) Fall time, CLKR/X CLKR/X int 1 1 ns MC11 tw(CKRXH) Pulse duration, CLKR/X high CLKR/X int D−2§ D+2§ D−1§ D+1§ ns MC12 tw(CKRXL) Pulse duration, CLKR/X low CLKR/X int C−2§ C+2§ C−1§ C+1§ ns MC13 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int −2 1 −2 1 ns MC13 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR ext 4 13 4 8 ns MC14 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX int −2 2 −2 2 ns MC14 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX ext 4 15 4 9 ns MC15 tdis(CKXH-DXHZ) Disable time, DX high-impedance from CLKX high CLKX int 0 5 −5 1 ns MC15 tdis(CKXH-DXHZ) Disable time, DX high-impedance from CLKX high following last data bit CLKX ext 10 18 3 11 ns Delay time, CLKX high to DX valid. CLKX int 5 4 Delay time, CLKX high to DX valid. This applies to all bits except the first bit transmitted. CLKX ext 15 9 MC16 t Delay time, CLKX high to DX valid¶ DXENA = 0 CLKX int 4 2 ns MC16 td(CKXH-DXV) valid¶ DXENA = 0 CLKX ext 13 7 ns Only applies to first bit transmitted when in Data Delay 1 or 2 DXENA = 1 CLKX int 2P + 1 2P + 1 when in Data Delay 1 or 2 (XDATDLY = 01b or 10b) modes DXENA = 1 CLKX ext 2P + 4 2P + 3 Enable time, DX driven from CLKX high¶ DXENA = 0 CLKX int −1 −3 MC17 ten(CKXH-DX) high¶ DXENA = 0 CLKX ext 6 3 ns MC17 ten(CKXH-DX) Only applies to first bit transmitted when in Data Delay 1 or 2 DXENA = 1 CLKX int P − 1 P − 3 ns when in Data Delay 1 or 2 (XDATDLY= 01b or 10b) modes DXENA = 1 CLKX ext P + 6 P + 3 Delay time, FSX high to DX valid¶ DXENA = 0 FSX int 2 2 MC18 td(FXH-DXV) Only applies to first bit transmitted DXENA = 0 FSX ext 13 8 ns MC18 td(FXH-DXV) Only applies to first bit transmitted when in Data Delay 0 (XDATDLY= DXENA = 1 FSX int 2P + 1 2P + 1 ns when in Data Delay 0 (XDATDLY= 00b) mode. DXENA = 1 FSX ext 2P + 10 2P + 10 Enable time, DX driven from FSX high¶ DXENA = 0 FSX int 0 0 MC19 ten(FXH-DX) high¶ DXENA = 0 FSX ext 8 3 ns MC19 ten(FXH-DX) Only applies to first bit transmitted when in Data Delay 0 (XDATDLY= DXENA = 1 FSX int P − 3 P − 3 ns when in Data Delay 0 (XDATDLY= 00b) mode DXENA = 1 FSX ext P + 8 P + 4 † Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns. § T=CLKRX period = (1 + CLKGDV) * P C=CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even D=CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even ¶ See the TMS320C55x DSP Peripherals Overview Reference Guide (literature number SPRU317) for a description of the DX enable (DXENA) and data delay features of the McBSP. |
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