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MB9B360L Datasheet(PDF) 101 Page - Cypress Semiconductor

Part # MB9B360L
Description  32-Bit Arm짰 Cortex짰-M4F FM4 Microcontroller
PDF  128 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

MB9B360L Datasheet(HTML) 101 Page - Cypress Semiconductor

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Document Number: 002-04930 Rev.*B
Page 101 of 128
MB9B360L Series
Fast Mode Plus (Fm+)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
Fast Mode Plus
(Fm+)*
6
Unit
Remarks
Min
Max
SCL clock frequency
FSCL
CL = 30 pF,
R = (Vp/IOL)*
1
0
1000
kHz
(Repeated) START condition hold time
SDA ↓ → SCL ↓
tHDSTA
0.26
-
μs
SCL clock "L" width
tLOW
0.5
-
μs
SCL clock "H" width
tHIGH
0.26
-
μs
SCL clock frequency
tSUSTA
0.26
-
μs
(Repeated) START condition hold time
SDA ↓ → SCL ↓
tHDDAT
0
0.45*
2, *3
μs
Data setup time
SDA ↓ ↑ → SCL ↑
tSUDAT
50
-
ns
STOP condition setup time
SCL ↑ → SDA ↑
tSUSTO
0.26
-
μs
Bus free time between
"STOP condition" and
"START condition"
tBUF
0.5
-
μs
Noise filter
tSP
60 MHz
≤
tCYCP<80 MHz
6 tCYCP*
4
-
ns
*5
80 MHz
≤
tCYCP<100 MHz
8 tCYCP*
4
-
ns
100 MHz
≤
tCYCP<120 MHz
10 tCYCP*
4
-
ns
120 MHz
≤
tCYCP<140 MHz
12 tCYCP*
4
-
ns
140 MHz
≤
tCYCP<160 MHz
14 tCYCP*
4
-
ns
160 MHz
≤
tCYCP<180 MHz
16 tCYCP*
4
-
ns
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power
supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal.
*3: A Fast-mode I
2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of
"tSUDAT
≥ 250 ns".
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I
2C is connected to, see 8. Block Diagram in this data sheet.
To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more.
*5: The noise filter time can be changed by register settings.
Change the number of the noise filter steps according to APB bus clock frequency.
*6: When using fast mode plus (Fm+), set the I/O pin to the mode corresponding to I
2C Fm+ in the EPFR register. See CHAPTER
12: I/O Port in FM4 Family Peripheral Manual Main part (002-04856) for the details.
tLOW
tHDSTA
tHDDAT
tHIGH
tSUDAT
tSUSTA
tHDSTA
tSP
tSUSTO
tBUF
SDA
SCL



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