MB9B360L datasheet(103/128 Pages) CYPRESS

103 / 128 page

Document Number: 002-04930 Rev.*B

Page 103 of 128

MB9B360L Series

12.5 12-bit A/D Converter

Electrical Characteristics for the A/D Converter

(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V)

Parameter

Symbol

Pin Name

Value

Unit

Remarks

Min

Typ

Max

Resolution

bit

Integral Nonlinearity

-4.5

+4.5

LSB

AVRH =

2.7 V to 5.5 V

Differential Nonlinearity

-2.5

+2.5

LSB

Zero transition voltage

VZT

AN00 to AN14

-15

+15

Full-scale transition voltage

VFST

AN00 to AN14

AVRH - 15

AVRH + 15

Conversion time

0.5*

μs

AVCC

≥ 4.5V

Sampling time

μs

AVCC

≥ 4.5V

AVCC < 4.5V

Compare clock cycle*

Tcck

1000

AVCC

≥ 4.5V

1000

AVCC < 4.5V

State transition time to

operation permission

Tstt

1.0

μs

Power supply current (analog

+ digital)

AVCC

0.69

0.92

A/D 1 unit operation

0.3

μA

When A/D stop

Reference power supply

current

(AVRH)

AVRH

1.1

1.97

A/D 1unit operation

AVRH=5.5 V

0.2

4.2

μA

When A/D stop

Analog input capacity

CAIN

Analog input resistance

RAIN

1.2

AVCC

≥ 4.5 V

1.8

AVCC < 4.5 V

Interchannel disparity

LSB

Analog port input leak current

AN00 to AN14

μA

Analog input voltage

AN00 to AN14

AVSS

AVRH

Reference voltage

AVRH

4.5

AVCC

Tcck < 50 ns

2.7

AVCC

Tcck ≥ 50 ns

*1: The conversion time is the value of sampling time (Ts) + compare time (Tc).

The condition of the minimum conversion time is when the value of sampling time: 150 ns, the value of compare time: 350 ns

(AVCC

≥ 4.5 V). Ensure that it satisfies the value of sampling time (Ts) and compare clock cycle (Tcck). For setting*4 of sampling

time and compare clock cycle, see CHAPTER 1-1: A/D Converter in FM4 Family Peripheral Manual Analog macro part

(002-04860). The register setting of the A/D Converter is reflected by the peripheral clock timing. The sampling and compare

clock are set at Base clock (HCLK).

*2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1).

*3: The compare time (Tc) is the value of (Equation 2).

*4: The register setting of the A/D Converter is reflected by the timing of the APB bus clock. The sampling clock and compare clock

are set in base clock (HCLK). About the APB bus number which the A/D Converter is connected to, see 8. Block Diagram in this

data sheet.

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