DLPC3470 datasheet(38/70 Pages) TI1

38 / 70 page

Pat

Pattern Display

Pat

Trigger Out 1

(Set Trigger)

Trigger Out 2

(Pattern Trigger)

Pat 0

Trigger In

(External)

Pattern Ready

(Output)

Pattern Data

Pat 1

Pat M

Blue

LED

Blue

LED

Blue

LED

Blue LED

BLUE LED

Illuminator

Pat

tD1

tD2

tDark

tExposure

tDark

tExposure

tDark

Load

tExposure

tDark

tExposure

tDark

tExposure

tD2

DLPC3470

DLPS110 – APRIL 2018

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Figure 22. Trigger In Mode

•

DLPC3470 controller sets the Pattern Ready signal high to denote that the DLPC3470 controller is ready to

accept external trigger signal.

•

User sends the external trigger signal to the DLPC3470 controller to start displaying next pattern with

predefined TExposure (exposure time) and TDark (dark time).

•

Blue LED is configured to be ON for each pattern.

•

TRIG_OUT_1 delay (tD1) is configured with reference to external trigger signal. TRIG_OUT_1 is set once

when Pattern Ready signal is high.

•

TRIG_OUT_2 delay (tD2) is configured with reference to external trigger signal. TRIG_OUT_2 is set once for

each 1D pattern.

8.3.2 Interface Timing Requirements

This section defines the timing requirements for the external interfaces for the DLPC3470 controller ASIC.

8.3.2.1 Parallel Interface

The parallel interface complies with standard graphics interface protocol, which includes a vertical syncronization

signal (VSYNC_WE), horizontal synchronization signal (HSYNC_CS), optional data valid signal (DATAEN_CMD),

a 24-bit data bus (PDATA), and a pixel clock (PCLK). The polarity of both syncs and the active edge of the clock

are programmable. Figure 4 shows the relationship of these signals. The data valid signal (DATAEN_CMD) is

optional in that the DLPC3470 controller provides auto-framing parameters that can be programmed to define the

data valid window based on pixel and line counting relative to the horizontal and vertical syncs.

In addition to these standard signals, an optional side-band signal (PDM_CVS_TE) is available, which allows

periodic frame updates to be stopped without losing the displayed image. When PDM_CVS_TE is active, it acts

as a data mask and does not allow the source image to be propagated to the display. A programmable PDM

polarity parameter determines if it is active high or active low. This parameter defaults to make PDM_CVS_TE

active high; if this function is not desired, then it should be tied to a logic low on the PCB. PDM_CVS_TE is

restricted to change only during vertical blanking.

NOTE

VSYNC_WE must remain active at all times (in lock-to-VSYNC mode) or the display

sequencer will stop and cause the LEDs to be turned off.

DLPC3470 Datasheet(PDF) 38 Page - Texas Instruments

DLPC3470 Datasheet(HTML) 38 Page - Texas Instruments

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