DLPC3470 datasheet(7/70 Pages) TI1

7 / 70 page

DLPC3470

www.ti.com

DLPS110 – APRIL 2018

Product Folder Links: DLPC3470

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(1)

PDATA(23:0) bus mapping is pixel format and source mode dependent. See later sections for details.

(2)

PDM_CVS_TE is optional for parallel interface operation. If unused, inputs should be grounded or pulled down to ground through an

external resistor (8 kΩ or less).

(3)

Pixel clock capture edge is software programmable.

(4)

The parallel data mask signal input is optional for parallel interface operations. If unused, inputs should be grounded or pulled down to

ground through an external resistor (8 kΩ or less).

(5)

Unused inputs should be grounded or pulled down to ground through an external resistor (8 kΩ or less).

(6)

VSYNC, HSYNC, and DATAEN polarity is software programmable.

Pin Functions – Parallel Port Input Data and Control(1)(2)

I/O

DESCRIPTION

NAME

NUMBER

PARALLEL RGB MODE

BT656 INTERFACE MODE

PCLK

I11

Pixel clock(3)

PDM_CVS_TE

Parallel data mask(4)

Unused(5)

VSYNC_WE

I11

Vsync(6)

Unused(5)

HSYNC_CS

I11

Hsync(6)

Unused(5)

DATAEN_CMD

I11

Data Valid(6)

Unused(5)

(TYPICAL RGB 888)

PDATA_0

PDATA_1

PDATA_2

PDATA_3

PDATA_4

PDATA_5

PDATA_6

PDATA_7

I11

Blue (bit weight 1)

Blue (bit weight 2)

Blue (bit weight 4)

Blue (bit weight 8)

Blue (bit weight 16)

Blue (bit weight 32)

Blue (bit weight 64)

Blue (bit weight 128)

BT656_Data (0)

BT656_Data (1)

BT656_Data (2)

BT656_Data (3)

BT656_Data (4)

BT656_Data (5)

BT656_Data (6)

BT656_Data (7)

(TYPICAL RGB 888)

PDATA_8

PDATA_9

PDATA_10

PDATA_11

PDATA_12

PDATA_13

PDATA_14

PDATA_15

I11

Green (bit weight 1)

Green (bit weight 2)

Green (bit weight 4)

Green (bit weight 8)

Green (bit weight 16)

Green (bit weight 32)

Green (bit weight 64)

Green (bit weight 128)

Unused

(TYPICAL RGB 888)

PDATA_16

PDATA_17

PDATA_18

PDATA_19

PDATA_20

PDATA_21

PDATA_22

PDATA_23

P10

I11

Red (bit weight 1)

Red (bit weight 2)

Red (bit weight 4)

Red (bit weight 8)

Red (bit weight 16)

Red (bit weight 32)

Red (bit weight 64)

Red (bit weight 128)

Unused

3DR

3D reference

•

For 3D applications: left or right 3D reference (left = 1, right = 0). To be provided by the

host when a 3D command is not provided. Must transition in the middle of each frame

(no closer than 1 ms to the active edge of VSYNC)

•

For light control applications: Reserved for external trigger signal (Input). Applicable in

Internal Pattern Streaming Mode only.

•

If a 3D or light control application is not being used (i.e. 3DR input is not being used),

then this input should be pulled low through an external resister (8K ohms or less).

Pin Functions – DMD Reset and Bias Control

I/O

DESCRIPTION

NAME

NUMBER

DMD_DEN_ARSTZ

DMD driver enable (active high) and DMD reset (active low). When the application

supplies the corresponding I/O power, this signal the device drives this signal low

after the DMD is parked and before power is removed from the DMD. If the 1.8-V

power to the DLPC3470 controller is independent of the 1.8-V power to the DMD,

then TI recommends a weak, external pulldown resistor to hold the signal low in the

event DLPC3470 controller power is inactive while DMD power is applied.

DMD_LS_CLK

DMD, low-speed interface clock

DLPC3470 Datasheet(PDF) 7 Page - Texas Instruments

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