DLPC3470 datasheet(58/70 Pages) TI1

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PLL_REFCLK_I

PLL_REFCLK_O

RFB

CL1

CL2

(Crystal)

DLPC3470

DLPS110 – APRIL 2018

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Layout Guidelines (continued)

11.1.2 DLPC3470 controller Reference Clock

The DLPC3470 controller requires an external reference clock to feed its internal PLL. A crystal or oscillator can

supply this reference. For flexibility, the DLPC3470 controller accepts either of two reference clock frequencies

(see Table 12), but both must have a maximum frequency variation of ±200 ppm (including aging, temperature,

and trim component variation). When a crystal is used, several discrete components are also required as shown

in Figure 36.

Figure 36. Required Discrete Components

CL1 = 2 × (CL – Cstray_pll_refclk_i)

(4)

CL2 = 2 × (CL – Cstray_pll_refclk_o)

where

•

CL is the crystal load capacitance (F

•

)

•

Cstray_pll_refclk_i is the sum of package and PCB stray capacitance at the crystal pin associated with the

ASIC pin, PLL_REFCLK_I

•

Cstray_pll_refclk_o is the sum of package and PCB stray capacitance at the crystal pin associated with the

ASIC pin PLL_REFCLK_O

(5)

11.1.2.1 Recommended Crystal Oscillator Configuration

Table 11. Crystal Port Characteristics

PARAMETER

NOM

UNIT

PLL_REFCLK_I TO GND capacitance

1.5

PLL_REFCLK_O TO GND capacitance

1.5

(1)

Temperature range of –30°C to +85°C

(2)

The crystal bias is determined by the ASIC's VCC_INTF voltage rail, which is variable (not the VCC18 rail).

Table 12. Recommended Crystal Configuration(1)(2)

PARAMETER

RECOMMENDED

UNIT

Crystal circuit configuration

Parallel resonant

Crystal type

Fundamental (first harmonic)

Crystal nominal frequency

MHz

Crystal frequency tolerance (including accuracy, temperature, aging and trim sensitivity)

±200

PPM

Maximum startup time

1.0

Crystal equivalent series resistance (ESR)

120 max

Crystal load

RS drive resistor (nominal)

100

RFB feedback resistor (nominal)

MΩ

DLPC3470 Datasheet(PDF) 58 Page - Texas Instruments

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