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DLPC3470 Datasheet(PDF) 53 Page - Texas Instruments |
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DLPC3470 Datasheet(HTML) 53 Page - Texas Instruments |
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53 / 70 page ![]() 53 DLPC3470 www.ti.com DLPS110 – APRIL 2018 Product Folder Links: DLPC3470 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated 10 Power Supply Recommendations 10.1 System Power-Up and Power-Down Sequence Although the DLPC3470 controller requires an array of power supply voltages, (for example, VDD, VDDLP12, VDD_PLLM/D, VCC18, VCC_FLSH, VCC_INTF), if VDDLP12 is tied to the 1.1-V VDD supply (which is assumed to be the typical configuration), then there are no restrictions regarding the relative order of power supply sequencing to avoid damaging the DLPC3470 controller . (This is true for both power-up and power-down scenarios). Similarly, there is no minimum time between powering-up or powering-down the different supplies if VDDLP12 is tied to the 1.1-V VDD supply. If however VDDLP12 is not tied to the VDD supply, then VDDLP12 must be powered-on after the VDD supply is powered-on, and powered-off before the VDD supply is powered-off. In addition, if VDDLP12 is not tied to VDD, then VDDLP12 and VDD supplies should be powered on or powered off within 100 ms of each other. Although there is no risk of damaging the DLPC3470 controller if the above power sequencing rules are followed, the following additional power sequencing recommendations must be considered to ensure proper system operation. • To ensure that DLPC3470 controller output signal states behave as expected, all DLPC3470 controller I/O supplies should remain applied while VDD core power is applied. If VDD core power is removed while the I/O supply (VCC_INTF) is applied, then the output signal state associated with the inactive I/O supply will go to a high impedance state. • Additional power sequencing rules may exist for devices that share the supplies with the DLPC3470 controller , and thus these devices may force additional system power sequencing requirements. Note that when VDD core power is applied, but I/O power is not applied, additional leakage current may be drawn. This added leakage does not affect normal DLPC3470 controller operation or reliability. Figure 33 and Figure 34 show the DLPC3470 controller power-up and power-down sequence for both the normal PARK and fast PARK operations of the DLPC3470 controller ASIC. |
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