DLPC3470 datasheet(42/70 Pages) TI1

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DLPC3470

DLPS110 – APRIL 2018

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8.3.2.3 Serial Flash Programming

Note that the flash can be programmed through the DLPC3470 controller over I2C or by driving the SPI pins of

the flash directly while the DLPC3470 controller I/O are tri-stated. SPI0_CLK, SPI0_DOUT, and SPI0_CSZ0 I/O

can be tri-stated by holding RESETZ in a logic low state while power is applied to the DLPC3470 controller .

Note that SPI0_CSZ1 is not tri-stated by this same action.

8.3.2.4 SPI Signal Routing

The DLPC3470 controller is designed to support two SPI slave devices on the SPI0 interface, specifically, a

serial flash and the DLPA2000 device . This requires routing associated SPI signals to two locations while

attempting to operate up to 36 MHz. Take special care to ensure that reflections do not compromise signal

integrity. To this end, the following recommendations are provided:

•

The SPI0_CLK PCB signal trace from the DLPC3470 controller source to each slave device should be split

into separate routes as close to the DLPC3470 controller as possible. In addition, the SPI0_CLK trace length

to each device should be equal in total length.

•

The SPI0_DOUT PCB signal trace from the DLPC3470 controller source to each slave device should be split

into separate routes as close to the DLPC3470 controller as possible. In addition, the SPI0_DOUT trace

length to each device should be equal in total length(use the same strategy as SPI0_CLK).

•

The SPI0_DIN PCB signal trace from each slave device to the point where they intersect on their way back to

the DLPC3470 controller should be made equal in length and as short as possible. They should then share a

common trace back to the DLPC3470 controller .

•

SPI0_CSZ0 and SPI0_CSZ1 need no special treatment because they are dedicated signals which drive only

one device.

8.3.2.5 I2C Interface Performance

Both DLPC3470 controller I2C interface ports support 100-kHz baud rate. By definition, I2C transactions operate

at the speed of the slowest device on the bus, thus there is no requirement to match the speed grade of all

devices in the system.

8.3.2.6 Content-Adaptive Illumination Control

Content-adaptive illumination control (CAIC) is an image processing algorithm that takes advantage of the fact

that in common real-world image content most pixels in the images are well below full scale for the for the R, G,

and B digital channels being input to the DLPC3470 controller . As a result of this the average picture level (APL)

for the overall image is also well below full scale, and the system’s dynamic range for the collective set of pixel

values is not fully utilized. CAIC takes advantage of this headroom between the source image APL and the top of

the available dynamic range of the display system.

CAIC evaluates images frame by frame and derives three unique digital gains, one for each of the R, G, and B

color channels. During CAIC image processing, each gain is applied to all pixels in the associated color channel.

CAIC derives each color channel’s gain that is applied to all pixels in that channel so that the pixels as a group

collectively shift upward and as close to full scale as possible. To prevent any image quality degradation, the

gains are set at the point where just a few pixels in each color channel are clipped. Figure 23 and Figure 24

show an example of the application of CAIC for one color channel.

DLPC3470 Datasheet(PDF) 42 Page - Texas Instruments

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