DLPC3470 datasheet(48/70 Pages) TI1

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DLPC3470

DLPS110 – APRIL 2018

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8.3.2.11 Calibration and Debug Support

The DLPC3470 controller contains a test point output port, TSTPT_(7:0), which provides selected system

calibration support, trigger support (TRIG_OUT_2) as well as ASIC debug support. These test points are inputs

while reset is applied and switch to outputs when reset is released. The state of these signals is sampled upon

the release of system reset and the captured value configures the test mode until the next time reset is applied.

Each test point includes an internal pulldown resistor, thus external pullups must be used to modify the default

test configuration. The default configuration (x000) corresponds to the TSTPT_(7:0) outputs remaining tri-stated

to reduce switching activity during normal operation. For maximum flexibility, an option to jumper to an external

pullup is recommended for TSTPT_(2:0). Pullups on TSTPT_(6:3) are used to configure the ASIC for a specific

mode or option. TI does not recommend adding pullups to TSTPT_(7:3) because this has adverse affects for

normal operation. This external pullup is only sampled upon a 0-to-1 transition on the RESETZ input, thus

changing their configuration after reset is released will not have any effect until the next time reset is asserted

and released. Table 10 defines the test mode selection for one programmable scenario defined by TSTPT(2:0).

(1)

These are only the default output selections. Software can reprogram the selection at any time.

Table 10. Test Mode Selection Scenario Defined by TSTPT(2:0)(1)

TSTPT(2:0) CAPTURE VALUE

NO SWITCHING ACTIVITY

CLOCK DEBUG OUTPUT

x000

x010

TSTPT(0)

HI-Z

60 MHz

TSTPT(1)

HI-Z

30 MHz

TSTPT(2)

HI-Z

0.7 to 22.5MHz

TSTPT(3)

HI-Z

HIGH

TSTPT(4)

HI-Z

LOW

TSTPT(5)

HI-Z

HIGH

TSTPT(6)

HI-Z

HIGH

TSTPT(7)

HI-Z

7.5 MHz

8.3.2.12 DMD Interface Considerations

The sub-LVDS HS interface waveform quality and timing on the DLPC3470 controller ASIC is dependent on the

total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses,

and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires

attention to many factors.

As an example, DMD interface system timing margin can be calculated as follows:

Setup Margin = (DLPC3470 controller output setup) – (DMD input setup) – (PCB routing mismatch) – (PCB SI

degradation)

(2)

Hold-time Margin = (DLPC3470 controller output hold) – (DMD input hold) – (PCB routing mismatch) – (PCB SI

degradation)

where PCB SI degradation is signal integrity degradation due to PCB affects which includes such things as

Simultaneously Switching Output (SSO) noise, cross-talk and Inter-symbol Interference (ISI) noise.

(3)

DLPC3470 controller I/O timing parameters as well as DMD I/O timing parameters can be found in their

corresponding data sheets. Similarly, PCB routing mismatch can be budgeted and met through controlled PCB

routing. However, PCB SI degradation is a more complicated adjustment.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design

guidelines are provided as a reference of an interconnect system that will satisfy both waveform quality and

timing requirements (accounting for both PCB routing mismatch and PCB SI degradation). Variation from these

recommendations may also work, but should be confirmed with PCB signal integrity analysis or lab

measurements.

DLPC3470 Datasheet(PDF) 48 Page - Texas Instruments

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