DLPC3470 datasheet(61/70 Pages) TI1

61 / 70 page

DLPC3470

www.ti.com

DLPS110 – APRIL 2018

Product Folder Links: DLPC3470

Submit Documentation Feedback

(1)

These values apply to PCB routing only. They do not include any internal package routing mismatch associated with the DLPC3470

controller , the DMD.

(2)

DMD HS data lines are differential, thus these specifications are pair-to-pair.

(3)

Training is applied to DMD HS data lines, so defined matching requirements are slightly relaxed.

(4)

DMD LS signals are single ended.

(5)

Mismatch variance applies to high-speed data pairs. For all high-speed data pairs, the maximum mismatch between pairs should be 1

mm or less.

Table 15. High Speed PCB Signal Routing Matching Requirements(1)(2)(3)(4)

SIGNAL GROUP LENGTH MATCHING

INTERFACE

SIGNAL GROUP

REFERENCE SIGNAL

MAX MISMATCH(5)

UNIT

DMD

DMD_HS_WDATA_A_P

DMD_HS_WDATA_A_N

DMD_HS_CLK_P

DMD_HS_CLK_N

±0.1

(±25.4)

inch

(mm)

DMD_HS_WDATA_B_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_C_P

DMD_HS_WDATA_C_N

DMD_HS_WDATA_D_P

DMD_HS_WDATA_D_N

DMD_HS_WDATA_E_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_H_P

DMD_HS_WDATA_H_N

DMD

DMD_LS_WDATA

DMD_LS_RDATA

DMD_LS_CLK

±0.2

(±5.08)

inch

(mm)

DMD

DMD_DEN_ARSTZ

N/A

inch

(mm)

11.1.6 Number of Layer Changes

•

Single-ended signals: Minimize the number of layer changes

•

Differential signals: Individual differential pairs can be routed on different layers, but the signals of a given pair

should not change layers.

11.1.7 Stubs

•

Stubs should be avoided.

11.1.8 Terminations

•

No external termination resistors are required on DMD_HS differential signals.

•

The DMD_LS_CLK and DMD_LS_WDATA signal paths should include a 43-Ω series termination resistor

located as close as possible to the corresponding ASIC pins.

•

The DMD_LS_RDATA signal path should include a 43-Ω series termination resistor located as close as

possible to the corresponding DMD pin.

•

DMD_DEN_ARSTZ does not require a series resistor.

11.1.9 Routing Vias

•

The number of vias on DMD_HS signals should be minimized and should not exceed two.

•

Any and all vias on DMD_HS signals should be located as close to the ASIC as possible.

•

The number of vias on the DMD_LS_CLK and DMD_LS_WDATA signals should be minimized and not

exceed two.

•

Any and all vias on the DMD_LS_CLK and DMD_LS_WDATA signals should be located as close to the ASIC

as possible.

DLPC3470 Datasheet(PDF) 61 Page - Texas Instruments

DLPC3470 Datasheet(HTML) 61 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Datasheet Download

Link URL