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T7906EKT/SC Datasheet(PDF) 1 Page - ATMEL Corporation |
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T7906EKT/SC Datasheet(HTML) 1 Page - ATMEL Corporation |
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1 / 42 page  Rev. A – 27-Aug.-01 1 Features • Besides the serial IEEE-1355 link, the T7906E provides several different interface types: – Host interface The host interface provides 8 multiplexed data and address lines to program and control the T7906E locally – FIFO interface The FIFO interface provides the control signals FULL, WRITE, EMPTY and READ depending on the direction of the data flow (receive / transmit) – ADC interface The ADC interface allows to connect an ADC with a width of up to 16 bits directly to the T7906E – DAC interface The DAC interface provides up to 16 bits data lines and the required control signals. The data to be sent to the DAC are stored until a command “start DAC” is received – RAM interface The RAM interface provides a 16-bit data bus and a 16-bit address bus. Four chip select allow to address 4 different memory partitions. The memory interface can be programmed to use up to 7 wait states – UART interface Two independent UART interfaces are included. One UART uses dedicated I/O lines whereas the second UART is sharing its pins with the GPIO port – General purpose I/O This general Purpose Interface provides up to 24 bidirectional signal lines. The direction of each GPIO line can be set individually via register – Timer / Event Counter Two 32-Bit on-chip timers are available. Each timer provides a 32-Bit counter and a 32-Bit reload register. The two timers can be operated independently or cascaded – JTAG (IEEE 1149.1) For testing purposes, a standard IEEE 1149.1 interface is provided. It supports the JTAG function Bypass, Extest, Sample/preload, All-tristate and IDCode • Designed on Atmel MG1090E sea of gates matrix and packaged into MQFPF100 • Also called SMCS Lite (or SMCS116) Description The T7906E provides one IEEE-1355 serial communication link with 0 to 200 Mbit/s data transmit rate. It supports both the standard IEEE-1355 link protocol (transparent mode) as well as the header generation required for the enhanced transaction layer of the TSS901E. This protocol uses specific protocol headers that can be generated by the T7906E without requiring an external host controller. These headers are stored in specific header registers which allows headers with a length of 0 (equaling the trans- parent mode) to eight bytes per packet. Packetization of data sent by the T7906E over the link is also done automatically according to the settings of a packet length register. Another feature provided by the transaction layer supported by the T7906E is an auto- matic checksum generation on the link. This is generated and checked automatically by the T7906E without requiring support from a host or other external source. Errors on the link are flagged and a special error packet is sent over the link to signal the error condition. Programming the T7906E internal registers is done via the IEEE-1355 link. All internal registers are 8-bit wide addressable. Two simple commands (read and write) suffice to access all functions and registers of the T7906E. Single Point to Point IEEE 1355 High Speed Controller T7906E |
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