TDA9554PS datasheet(23/125 Pages) PHILIPS

23 / 125 page

2000 Jun 22

Philips Semiconductors

Tentative Device Speciﬁcation

TV signal processor-Teletext decoder with

embedded

µ-Controller

TDA955X/6X/8X PS/N1 series

M1,M0

Mode Control bits Timer/Counter 0.

M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 pre-scaler.

M1,M0 = 01, 16 bit time interval or event counter.

M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overﬂow. Reload value stored in TH0.

M1,M0 = 11, one 8 bit time interval or event counter and one 8 bit time interval counter.

TP2CL

TP2CL<7>

TP2CL<6>

TP2CL<5>

TP2CL<4>

TP2CL<3>

TP2CL<2>

TP2CL<1>

TP2CL<0>

00H

TP2CL<7:0>

Indicate the low byte of the Time 2 current value.

TP2CH

TP2CH<7>

TP2CH<6>

TP2CH<5>

TP2CH<4>

TP2CH<3>

TP2CH<2>

TP2CH<1>

TP2CH<0>

00H

TP2CH<7:0>

Indicate the high byte of the Time 2 current value.

TP2H

TP2H<7>

TP2H<6>

TP2H<5>

TP2H<4>

TP2H<3>

TP2H<2>

TP2H<1>

TP2H<0>

00H

TP2H<7:0>

Timer 2 high byte, never change unless updated by the software.

TP2L

TP2L<7>

TP2L<6>

TP2L<5>

TP2L<4>

TP2L<3>

TP2L<2>

TP2L<1>

TP2L<0>

00H

TP2L<7:0>

Timer 2 low byte, never change unless updated by the software.

TP2PR

TP2PR<7>

TP2PR<6>

TP2PR<5>

TP2PR<4>

TP2PR<3>

TP2PR<2>

TP2PR<1>

TP2PR<0>

00H

TP2H<7:0>

Timer 2 Pre-scaler, never change unless updated by the software.

TP2CRL

------

TP2CRL<1>

TP2CRL<0>

00H

TP2CRL<0>

Timer 2 Control.

0 - Timer 2 disabled.

1 - Timer 2 enabled.

TP2CRL<1>

Timer 2 Status.

0 - No Overﬂow.

1 - Overﬂow.

TEST

TEST<7>

TEST<6>

TEST<5>

TEST<4>

TEST<3>

TEST<2>

TEST<1>

TEST<0>

00H

TEST<2:0>

Program Type bit SEL<2:0>.

011 - Display Dram test.

001 - Acquisition1 test.

010 - Acquisition2 test

TEST<4:3>

Functional test mode bits, set via mode select logic.

TEST<7:5>

Dram Size.

000 - 1.5K x 16.

001 - 2K x 16.

010 - 6K x 16.

011 - 7K x 16.

100 - 12K x 16.

101 - 14K x 16.

110 - 1K x 16.

111 - 11K x 16.

TXT0

X24 POSN

DISPLAY

X24

AUTO

FRAME

DISABLE

HEADER

ROLL

DISPLAY

STATUS

ROW

ONLY

DISABLE

FRAME

VPS ON

INV ON

00H

X24 POSN

0 - Store X/24 in extension memory

1 - Store X/24 in basic page memory with packets 0 to 23

Names

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

RESET

Table 3

SFR Bit description

TDA9554PS Datasheet(PDF) 23 Page - NXP Semiconductors

TDA9554PS Datasheet(HTML) 23 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL