MMPF0100Z datasheet(17/128 Pages) NXP

17 / 128 page

NXP Semiconductors

PF0100Z

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Functional block requirements and behaviors

6.1

Start-up

The PF0100Z can be configured to start-up from either the internal OTP configuration, or with a hard-coded configuration built in to the

device. The internal hard-coded configuration is enabled by connecting the VDDOTP pin to VCOREDIG through a 100 k

Ω resistor. The

OTP configuration is enabled by connecting VDDOTP to GND.

For NP devices, selecting the OTP configuration causes the PF0100Z not to start-up. However, the PF0100Z can be controlled through

the I2C port for prototyping and programming. Once programmed, the NP device starts up with the customer programmed configuration.

6.1.1

Device start-up configuration

Table 9 shows the default configuration, which can be accessed on all devices as described previously, as well as the pre-programmed

OTP configurations.

Table 9. Start-up configuration

Registers

Default

configuration

Pre-programmed OTP configuration

All devices

Default I2C Address

0x08

VSNVS_VOLT

3.0 V

3.0 V3.0 V3.0 V

SW1AB_VOLT

1.375 V

1.425 V

1.375 V

SW1AB_SEQ

SW1C_VOLT

1.375 V

1.425 V

1.375 V

SW1C_SEQ

SW2_VOLT

3.0 V

3.3 V

3.0 V

1.375 V

SW2_SEQ

SW3A_VOLT

1.5 V

1.35 V

1.5 V

1.350 V

1.5 V

SW3A_SEQ

SW3B_VOLT

1.5 V

1.35 V

1.5 V

1.350 V

1.5 V

SW3B_SEQ

SW4_VOLT

1.8 V

3.15 V

1.8 V

3.15 V

1.825 V

SW4_SEQ

-7

SWBST_VOLT

5.0 V

SWBST_SEQ

Off

-10

VREFDDR_SEQ

VGEN1_VOLT

1.5 V

1.2 V

1.5 V1.2 V1.2 V

VGEN1_SEQ

VGEN2_VOLT

1.5 V

1.5 V1.5 V1.5 V

VGEN2_SEQ

Off

-8

VGEN3_VOLT

2.5 V

2.8 V

2.5 V1.8 V1.8 V

VGEN3_SEQ

-8

VGEN4_VOLT

1.8 V

1.8 V3.0 V3.0 V

VGEN4_SEQ

-4

MMPF0100Z Datasheet(PDF) 17 Page - NXP Semiconductors

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