MMPF0100Z datasheet(91/128 Pages) NXP

91 / 128 page

NXP Semiconductors

PF0100Z

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Figure 26. VSNVS supply switch architecture

Table 107 provides a summary of the VSNVS operation at a different VIN input voltage and with or without coin cell connected to the

system.

6.4.7.0.1

VSNVS control

The VSNVS output level is configured through the VSNVSVOLT[2:0]bits on VSNVSCTL register as shown in table Table 108.

6.4.7.0.2

VSNVS external components

Table 107. VSNVS modes of operation

VSNVSVOLT[2:0]

VIN

Mode

110

> VTH1

VIN LDO 3.0 V

110

< VTL1

Coin cell switch

000 – 101

> VTH0

VIN LDO

000 – 101

< VTL0

Coin cell LDO

Table 108. Register VSNVSCTL - ADDR 0x6B

Name

Bit #

R/W

Default

Description

VSNVSVOLT

2:0

R/W

0x80

Configures VSNVS output voltage.(73)

000 = 1.0 V

001 = 1.1 V

010 = 1.2 V

011 = 1.3 V

100 = 1.5 V

101 = 1.8 V

110 = 3.0 V

111 = RSVD

UNUSED

7:3

–

0x00

unused

Notes

73.

Only valid when a valid input voltage is present.

Table 109. VSNVS external components

Capacitor

Value (

μF)

VSNVS

0.47

LDO\

PF0100Z

VSNVS

Coin Cell

1.8 - 3.3 V

VIN

2.25 V (VTL0) -

4.5 V

LICELL

Charger

LDO/SWITCH

VREF

Input

Sense/

Selector

2C Interface

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