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MMPF0100Z Datasheet(PDF) 19 Page - NXP Semiconductors |
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MMPF0100Z Datasheet(HTML) 19 Page - NXP Semiconductors |
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19 / 128 page ![]() NXP Semiconductors 19 PF0100Z FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Figure 6. Default start-up sequence Table 10. Default start-up sequence timing Parameter Description Min. Typ. Max. Unit Notes tD1 Turn-on delay of VSNVS – 5.0 – ms (23) tR1 Rise time of VSNVS – 3.0 – ms tD2 User determined delay – 1.0 – ms tR2 Rise time of PWRON – (24) –ms tD3 Turn-on delay of first regulator SEQ_CLK_SPEED[1:0] = 00 –2.0 – ms SEQ_CLK_SPEED[1:0] = 01 –2.5 – (25) SEQ_CLK_SPEED[1:0] = 10 –4.0 – SEQ_CLK_SPEED[1:0] = 11 –7.0 – tR3 Rise time of regulators – 0.2 – ms (26) *VSNVS starts from 1.0 V if LICELL is valid before VIN. UVDET LICELL VIN VSNVS PWRON SW1A/B SW1C SW2 VGEN2 SW3A/B SW4 VREFDDR VGEN4 VGEN5 VGEN6 RESETBMCU td1 td3 td4 td4 tr1 tr3 tr3 tr3 td5 tr4 tr2 td2 1V |
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