MMPF0100Z datasheet(78/128 Pages) NXP

78 / 128 page

NXP Semiconductors

PF0100Z

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

For more detail information, Table 94 through Table 99 provide a description of all registers necessary to operate all six general purpose

LDO regulators.

Table 93. LDO control

VGENxEN

VGENxLPWR

VGENxSTBY

STANDBY(61)

VGENxOUT

Off

Low Power

Off

Low Power

Notes

61.

STANDBY refers to a standby event as described earlier.

Table 94. Register VGEN1CTL - ADDR 0x6C

Name

Bit #

R/W

Default

Description

VGEN1

3:0

R/W

0x80

Sets VGEN1 output voltage.

See Table 91 for all possible configurations.

VGEN1EN

–

0x00

Enables or disables VGEN1 output

0 = OFF

1 = ON

VGEN1STBY

R/W

0x00

Set VGEN1 output state when in standby. Refer

to Table 93.

VGEN1LPWR

R/W

0x00

Enable low-power mode for VGEN1. Refer to

Table 93.

UNUSED

–

0x00

unused

Table 95. Register VGEN2CTL - ADDR 0x6D

Name

Bit #

R/W

Default

Description

VGEN2

3:0

R/W

0x80

Sets VGEN2 output voltage.

See Table 91 for all possible configurations.

VGEN2EN

–

0x00

Enables or disables VGEN2 output

0 = OFF

1 = ON

VGEN2STBY

R/W

0x00

Set VGEN2 output state when in standby. Refer

to Table 93.

VGEN2LPWR

R/W

0x00

Enable low-power mode for VGEN2. Refer to

Table 93.

UNUSED

–

0x00

unused

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