MMPF0100Z datasheet(73/128 Pages) NXP

73 / 128 page

NXP Semiconductors

PF0100Z

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Figure 23. Boost Regulator Architecture

6.4.5.1

SWBST setup and control

Boost regulator control is done through a single register SWBSTCTL described in Table 87. SWBST is included in the power-up sequence

if its OTP power-up timing bits, SWBST_SEQ[4:0], are not all zeros.

Table 87. Register SWBSTCTL - ADDR 0x66

Name

Bit #

R/W

Default

Description

SWBST1VOLT

1:0

R/W

0x00

Set the output voltage for SWBST

00 = 5.000 V

01 = 5.050 V

10 = 5.100 V

11 = 5.150 V

SWBST1MODE

3:2

0x02

Set the switching mode on normal operation

00 = OFF

01 = PFM

10 = Auto (Default)(58)

11 = APS

UNUSED

–

0x00

unused

SWBST1STBYMODE

6:5

R/W

0x02

Set the switching mode on standby

00 = OFF

01 = PFM

10 = Auto (Default)(58)

11 = APS

UNUSED

–

0x00

unused

Notes

58.

In auto mode, the controller automatically switches between PFM and APS modes depending on the load current.

The SWBST regulator starts up by default in the auto mode, if SWBST is part of the startup sequence.

SWBSTLX

VOBST

Driver

Controller

Internal

Compensation

I2C

Interface

SWBSTMODE

VREFUV

VREF

VIN

LBST

CINBST

DBST

SWBSTFB

RSENSE

VREFSC

SWBSTFAULT

COSWBST

SWBSTIN

MMPF0100Z Datasheet(PDF) 73 Page - NXP Semiconductors

MMPF0100Z Datasheet(HTML) 73 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL