MMPF0100Z datasheet(27/128 Pages) NXP

27 / 128 page

NXP Semiconductors

PF0100Z

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.4

Power generation

6.4.1

Modes of operation

The operation of the PF0100Z can be reduced to five states, or modes: on, off, sleep, standby, and coin cell. Figure 8 shows the state

diagram of the PF0100Z, along with the conditions to enter and exit from each state.

Figure 8. State diagram

To complement the state diagram in Figure 8, a description of the states is provided in following sections. Note that VIN must exceed the

rising UVDET threshold to allow a power up. Refer to Table 28 for the UVDET thresholds. Additionally, I2C control is not possible in the

coin cell mode and the interrupt signal, INTB, is only active in sleep, standby, and on states.

6.4.1.1

On mode

The PF0100Z enters the on mode after a turn-on event. RESETBMCU is de-asserted, high, in this mode of operation.

6.4.1.2

Off mode

The PF0100Z enters the off mode after a turn-off event. A thermal shutdown event also forces the PF0100Z into the off mode. Only

VCOREDIG and VSNVS are powered in the mode of operation. To exit the off mode, a valid turn-on event is required. RESETBMCU is

asserted, low, in this mode.

PWRON = 0 held >= 4.0 sec

Any SWxOMODE bits=1

& PWRONRSTEN = 1

(PWRON_CFG=1)

PWRON=1

& VIN > UVDET

(PWRON_CFG =0)

PWRON= 0 < 4.0 sec

& VIN > UVDET

(PWRON_CFG=1)

PWRON = 0

Any SWxOMODE bits=1

(PWRON_CFG=0)

PWRON=0 held >= 4.0 sec

Any SWxOMODE bits=1

& PWRONRSTEN = 1

(PWRON_CFG=1)

PWRON=1

& VIN > UVDET

(PWRON_CFG = 0)

PWRON= 0 < 4.0 sec

& VIN > UVDET

(PWRON_CFG=1)

PWRON = 0

All SWxOMODE bits= 0

(PWRON_CFG = 0)

PWRON = 0 held >= 4.0 sec

All SWxOMODE bits= 0

& PWRONRSTEN = 1

(PWRON_CFG = 1)

OFF

Sleep

Coin Cell

VIN < UVDET

VIN > UVDET

Thermal shudown

Standby

STANDBY asserted

VIN < UVDET

Thermal shutdown

STANDBY de-asserted

PWRON = 0

Any SWxOMODE bits=1

(PWRON_CFG=0)

PWRON=0 held >= 4.0 sec

Any SWxOMODE bits=1

& PWRONRSTEN = 1

(PWRON_CFG=1)

PWRON = 0

All SWxOMODE bits= 0

(PWRON_CFG = 0)

PWRON = 0 held >= 4.0 sec

All SWxOMODE bits= 0

& PWRONRSTEN = 1

(PWRON_CFG = 1)

VIN < UVDET

MMPF0100Z Datasheet(PDF) 27 Page - NXP Semiconductors

MMPF0100Z Datasheet(HTML) 27 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL