MMPF0100Z datasheet(90/128 Pages) NXP

90 / 128 page

NXP Semiconductors

PF0100Z

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.4.7

VSNVS LDO/switch

VSNVS powers the low-power, SNVS/RTC domain on the processor. It derives its power from either VIN, or coin cell, and cannot be

disabled. When powered by both, VIN takes precedence when above the appropriate comparator threshold. When powered by VIN,

VSNVS is an LDO capable of supplying seven voltages: 3.0, 1.8, 1.5, 1.3, 1.2, 1.1, and 1.0 V. The bits VSNVSVOLT[2:0] in register

VSNVS_CONTROL determine the output voltage. When powered by coin cell, VSNVS is an LDO capable of supplying 1.8, 1.5, 1.3, 1.2,

1.1, or 1.0 V as shown in Table 107. If the 3.0 V option is chosen with the coin cell, VSNVS tracks the coin cell voltage by means of a

switch, whose maximum resistance is 100

Ω. In this case, the VSNVS voltage is simply the coin cell voltage minus the voltage drop across

the switch, which is 40 mV at a rated maximum load current of 400

μA.

The default setting of the VSNVSVOLT[2:0] is 110, or 3.0 V, unless programmed otherwise in OTP. However, when the coin cell is applied

for the very first time, VSNVS outputs 1.0 V. Only when VIN is applied thereafter, VSNVS transitions to its default, or the programmed value

if different. Upon subsequent removal of VIN, with the coin cell attached, VSNVS changes configuration from an LDO to a switch for the

“110” setting, and remains as an LDO for the other settings, continuing to output the same voltages as when VIN is applied, providing

certain conditions are met as described in Table 107.

VGEN6 AC and transient (continued)

GEN6tON

Turn-on time

Enable to 90% of end value, VIN3 = VIN3MIN, 4.5 V

IGEN6 = 0.0 mA

–

500

μs

GEN6tOFF

Turn-off time

Disable to 10% of initial value, VIN3 = VIN3MIN

IGEN6 = 0.0 mA

––

GEN6OSHT

Start-up overshoot

VIN3 = VIN3MIN, 4.5 V, IGEN6 = 0 mA

–1.0

2.0

VGEN6LOTR

Transient load response

VIN3 = VIN3MIN, 4.5 V

IGEN6 = 20 to 200 mA in 1.0 μs

Peak of overshoot or undershoot of VGEN6 with respect to final

value. Refer to Figure 25

––

3.0

VGEN6LITR

Transient line response

IGEN6 = 150 mA

VIN3INITIAL = 2.8 V to VIN3FINAL = 3.3 V for

VGEN6[3:0] = 0000 to 0111

VIN3INITIAL = VGEN6+0.3 V to VIN3FINAL = VGEN6+0.8 V for

VGEN6[3:0] = 1000 to 1111

Refer to Figure 25

–5.0

8.0

Notes

71.

When the LDO output voltage is set above 2.6 V, the minimum allowed input voltage needs to be at least the output voltage plus 0.25 V for proper

regulation due to the dropout voltage generated through the internal LDO transistor.

72.

The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately

from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout

region of the regulator under test. VIN3MIN refers to the minimum allowed input voltage for a particular output voltage.

Table 106. VGEN6 electrical characteristics (continued)

All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN3 = 3.6 V,

VGEN6[3:0] = 1111, IGEN6 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at

VIN = 3.6 V, VIN3 = 3.6 V, VGEN6[3:0] = 1111, IGEN6 = 10 mA, and 25 °C, unless otherwise noted.

Symbol

Parameter

Min

Typ

Max

Unit

Notes

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