SCD1284 datasheet(76/176 Pages) INTEL

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CD1284 — IEEE 1284-Compatible Parallel Interface Controller

Datasheet

5.11.6

Stale Data (Stale, OneChar, and Timeout Status Bits)

Data transfer to the CPU can also be initiated by the ‘stale’ data timer. This timer is reloaded with

the value in the SDTPR and restarts each time data is placed into the FIFO from the parallel port.

When the timer reaches zero, the status indication stale (visible in the PFSR) is set true unless

StaleOff (PACR[5]) is true.

StaleOff keeps the stale status false, even though the SDTCR counter value is zero. Should the stale

status become true with at least two characters of data available, a DMA request is made to transfer

the data. If the stale is true and there is exactly one character available, the OneChar status bit is set

(PFSR[1]) and an interrupt is generated to the CPU to transfer the single residual character.

The Parallel FIFO Status register indicates the Stale and OneChar conditions, and FFmpty. The

HRSR (Holding Register Status register) shows that holding register PFHR2 contains the final

character. An odd number of bytes can not be transferred by DMA. If a DMA transfer completes

with 1 byte of data left, the data is held pending arrival of additional data or the expiration of the

stale data timer.

The OneChar status is latched true when the FIFO and DMA buffer are empty and there is one

character in the pipeline in PFHR2. While the OneChar status is true, further pipeline operations

are inhibited. If additional data arrives in the FIFO, it remains there until the CPU:

1. Services the interrupt caused by the OneChar status, and

2. Reads the data character from PFHR2.

When the CPU reads the single character from PFHR2, any newly arrived data in the FIFO

immediately moves forward into the pipeline and a DMA transfer can begin if conditions warrant.

Another latched status condition associated with the stale data timer is the Timeout status bit

(PFSR[5]). Timeout is reset by the FIFOres bit (PFCR[7]) and the ClrTO bit (PACR[3]). Timeout,

OneChar, and DataErr are pipeline interrupt conditions and, if enabled, generate an interrupt. In the

receive direction, the Timeout condition is armed when Stale is ‘0’ and ClrTO and FIFOres are also

‘0’. When Stale becomes ‘1,’ the timeout is triggered, but is not set until a DMA transfer is

complete, the FIFO is empty, and there is no more than one character remaining in the pipeline. To

clear the timeout condition, set the ClrTO bit. To reenable the timeout function, clear the ClrTO bit.

The CPU can arm the timeout by a write of ‘01h’ directly to the SDTCR. If the timer expires before

any data arrives, an interrupt is generated for the timeout condition. If data arrives before the timer

expires, the interrupt delays until the data becomes stale.

5.11.7

Transmit Direction

Note:

In the transmit direction, the pipeline behaves in one of two ways depending on the RLEen control

bit. RLEen should only be set by the CPU after the parallel port is in ECP mode, otherwise

compression of data occurs, but cannot be supported in data transfers on the parallel port. If RLEen

is ‘0’, data written to the DMABUF register by a DMA (DMAen true) or CPU write (DMAbufWe

true) is moved through PFHR1 to PFHR2 and immediately transferred into the FIFO (if space is

available).

If RLEen is ‘1’, run-length encoding is enabled and comparators among the pipeline stages

recognize repeated strings of characters and compress them (Figure 12 on page 80). To allow the

comparator-based logic to work, the pipeline registers, PFHR1 and PFHR2, must be kept full. One

comparator determines if the characters in PFHR1 and PFHR2 are identical.

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