SCD1284 datasheet(20/176 Pages) INTEL

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CD1284 — IEEE 1284-Compatible Parallel Interface Controller

Datasheet

RXD3

TXD2

High

RXD2

RTS2*

High

RTS3*

High

DTR2*

High

DTR3*

High

CTS2*

CTS3*

DSR2*

DSR3*

CD2*

CD3*

RI2*

RI3*

N/C

–

174

Table 1.

Pin Descriptions (Sheet 1 of 4)

Symbol

Pin No.

Type

Description

RESET*

ACTIVE-LOW RESET: This input initializes the device to the default condition. All

internal registers are set to their reset condition and all transfer operations are set to

the default state.

OUTEN

OUTPUT ENABLE: This pin must be ‘1’ to enable output pin functions. When OUTEN

is ‘0’, it forces all output pins to remain in a tristate condition. Typically, OUTEN is used

only for test purposes. User designs must tie this pin to VCC through a pull-up resistor.

CLK

SYSTEM CLOCK: This input has a 25-MHz maximum; 16 MHz is the recommended

minimum for satisfactory device performance.

CLK/2

SYSTEM CLOCK DIVIDED BY TWO OUTPUT: This signal is equivalent to the

internal operating clock of the device.

DB[15:0]

92–99, 2–9I/O

BIDIRECTIONAL DATA BUS: Only DMA transfers and writes to the DMA Buffer

Buffer register, bits [7:0] are written to the addressed register. Register reads duplicate

the register contents on both the lower byte [7:0] and upper byte [15:8].

A[6:0]

84–90

ADDRESS BUS: Together with CS* or one of the SVCACK* inputs and DS*, this input

selects an On-Chip register for a read or write operation or an acknowledgment to an

service request.

R/W*

READ/WRITE*: This input must be ‘1’ for a register read operation, and must be ‘0’ for

a register write. R/W* is ignored for DMA operations.

CS*

ACTIVE-LOW CHIP SELECT: When active, the input CS* combines with DS*,

initiates an I/O cycle with the CD1284. CS* must be ‘1’ during DMA read/write

operations.

Pin Name

Type

Number

of Pins

Number

Reset

State

(Sheet 3 of 3)

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