NT5CC64M16GP-DINA datasheet(83/160 Pages) NANYA

83 / 160 page

Version 2.2

Nanya Technology Cooperation ©

04/2019

NTC Proprietary

Level: Property

DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

Asynchronous to Synchronous ODT Mode during short CKE high and short CKE low

periods

If the total time in Precharge Power Down state or Idle state is very short, the transition periods for PD entry and PD exit

may overlap. In this case, the response of the DDR3(L) SDRAMs RTT to a change in ODT state at the input may be

synchronous or asynchronous from the state of the PD entry transition period to the end of the PD exit transition period

(even if the entry ends later than the exit period).

If the total time in Idle state is very short, the transition periods for PD exit and PD entry may overlap. In this case, the

response of the DDR3(L) SDRAMs RTT to a change in ODT state at the input may be synchronous or asynchronous from

the start of the PD exit transition period to the end of the PD entry transition period. Note that in the following figure, it is

assumed that there was no Refresh command in progress when Idle state was entered.

Transition period for short CKE cycles with entry and exit period overlapping

(AL=0; WL=5; tANPD=WL-1=4)

T11

T10

T12

T13

T14

tANPD

Do not

care

Transitioning

CKE

CMD

REF

NOP

PD exit transition period

tANPD

tXPDLL

PD entry transition period

tRFC(min)

CKE

Short CKE high transition period

tXPDLL

NT5CC64M16GP-DINA Datasheet(PDF) 83 Page - Nanya Technology Corporation.