NT5CC64M16GP-DINA datasheet(99/160 Pages) NANYA

99 / 160 page

Version 2.2

Nanya Technology Cooperation ©

04/2019

NTC Proprietary

Level: Property

DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

Single-ended levels for CK, DQS, DQSL, DQSU,

, , L, or U

Symbol

Parameter

DDR3-800, DDR3(L)-1066, 1333, 1600, 1866

Unit

Notes

Min.

Max.

VSEH

Single-ended high-level for strobes

(VDDQ/2) + 0.175

note3

1, 2

Single-ended high-level for CK,



(VDDQ/2) + 0.175

note3

1, 2

VSEL

Single-ended low-level for strobes

note3

(VDDQ/2) - 0.175

1, 2

Single-ended Low-level for CK,



note3

(VDDQ/2) - 0.175

1, 2

Note:

1. For CK,

 use VIH/VIL(ac) of ADD/CMD; for strobes (DQS, DQSL, DQSU, CK, , L, or U) use VIH/VIL(ac) of DQs.

2. VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VIH(ac)/VIL(ac) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low

level is used for a signal group, then the reduced level applies also there.

3. These values are not defined, however the single-ended signals CK,

, DQS, , DQSL, L, DQSU, U need to be within

the respective limits (VIH(dc)max, VIL(dc)min) for single-ended signals as well as limitations for overshoot and undershoot.

NT5CC64M16GP-DINA Datasheet(PDF) 99 Page - Nanya Technology Corporation.

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