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AD9174 Datasheet(PDF) 83 Page - Analog Devices

Part # AD9174
Description  Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer
PDF  164 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9174 Datasheet(HTML) 83 Page - Analog Devices

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Data Sheet
AD9174
Rev. A | Page 83 of 164
Reg.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RW
0x085
NVM_CTRL1
RESERVED
NVM_CTRL1A
RESERVED
NVM_
CTRL1B
NVM_
CTRL1C
0x13
R/W
0x08D
ADC_CLK_
CTRL0
RESERVED
CLKOUT_SWING
0x00
R/W
0x08F
ADC_CLK_
CTRL2
RESERVED
PD_
CLKOUT_
DRIVER
0x00
R/W
0x090
DAC_
POWERDOWN
RESERVED
DAC_PD1
DAC_PD0
0x03
R/W
0x091
ACLK_CTRL
RESERVED
ACLK_
POWER-
DOWN
0x01
R/W
0x094
PLL_CLK_DIV
RESERVED
PLL_VCO_
DIV3_EN
PLL_VCO_
DIV2_EN
0x00
R/W
0x095
PLL_BYPASS
RESERVED
PLL_
BYPASS
0x00
R/W
0x09A
NVM_CTRL
PD_BGR
RESERVED
0x00
R/W
0x0C0
DELAY_LINE_PD
RESERVED
DLL_CTRL0B
DLL_CTRL0A
RESERVED
DLL_PD
0x31
R/W
0x0C1
DLL_CTRL0
DLL_CTRL1C
DLL_CTRL1B
DLL_CTRL1A
RESERVED
DLL_
ENABLE
0x70
R/W
0x0C3
DLL_STATUS
RESERVED
DLL_LOCK
0x00
R/W
0x0C7
DLL_READ
RESERVED
DLL_
READ_EN
0x00
R/W
0x0CC
DLL_FINE_
DELAY0
RESERVED
DLL_FINE_DELAY0
0x00
R/W
0x0CD
DLL_FINE_
DELAY1
RESERVED
DLL_FINE_DELAY1
0x00
R/W
0x0DB
DLL_UPDATE
RESERVED
DLL_
DELAY_
UPDATE
0x00
R/W
0x0FF
MOD_SWITCH_
DEBUG
RESERVED
CMPLX_
MOD_DIV2_
DISABLE
RESERVED
0x00
R/W
0x100
DIG_RESET
RESERVED
DIG_
DATAPATH_
PD
0x01
R/W
0x110
JESD_MODE
MODE_NOT_
IN_TABLE
COM_SYNC
JESD_MODE
0x20
R/W
0x111
INTRP_MODE
DP_INTERP_MODE
CH_INTERP_MODE
0x84
R/W
0x112
DDSM_
DATAPATH_CFG
RESERVED
EN_CMPLX_
MOD
DDSM_MODE
DDSM_
NCO_EN
DDSM_
MODULUS_
EN
DDSM_SEL_
SIDEBAND
EN_SYNC_
ALL_CHNL_
NCO_
RESETS
0x01
R/W
0x113
DDSM_FTW_
UPDATE
RESERVED
DDSM_FTW_REQ_MODE
RESERVED
DDSM_
FTW_
LOAD_
SYSREF
DDSM_
FTW_
LOAD_ACK
DDSM_
FTW_
LOAD_REQ
0x00
R/W
0x114
DDSM_FTW0
DDSM_FTW[7:0]
0x00
R/W
0x115
DDSM_FTW1
DDSM_FTW[15:8]
0x00
R/W
0x116
DDSM_FTW2
DDSM_FTW[23:16]
0x00
R/W
0x117
DDSM_FTW3
DDSM_FTW[31:24]
0x00
R/W
0x118
DDSM_FTW4
DDSM_FTW[39:32]
0x00
R/W
0x119
DDSM_FTW5
DDSM_FTW[47:40]
0x00
R/W
0x11C
DDSM_PHASE_
OFFSET0
DDSM_NCO_PHASE_OFFSET[7:0]
0x00
R/W
0x11D
DDSM_PHASE_
OFFSET1
DDSM_NCO_PHASE_OFFSET[15:8]
0x00
R/W
0x124
DDSM_ACC_
MODULUS0
DDSM_ACC_MODULUS[7:0]
0x00
R/W
0x125
DDSM_ACC_
MODULUS1
DDSM_ACC_MODULUS[15:8]
0x00
R/W
0x126
DDSM_ACC_
MODULUS2
DDSM_ACC_MODULUS[23:16]
0x00
R/W
0x127
DDSM_ACC_
MODULUS3
DDSM_ACC_MODULUS[31:24]
0x00
R/W
0x128
DDSM_ACC_
MODULUS4
DDSM_ACC_MODULUS[39:32]
0x00
R/W
0x129
DDSM_ACC_
MODULUS5
DDSM_ACC_MODULUS[47:40]
0x00
R/W
0x12A
DDSM_ACC_
DELTA0
DDSM_ACC_DELTA[7:0]
0x00
R/W



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