© VITESSE SEMICONDUCTOR CORPORATION

Page 5

12/1/99

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC8151

2.488Gb/s SONET/SDH

STS-48/STM-16 Section Terminator

G52225-0, Rev. 2.9

If the user chooses to use the CDR as a timing source even during AIS mode, the output of the CDR can be

connected single ended to both RXSCLKIN and TXSCLKIN, or a multi-drop connection can be made differen-

tially.

Figure 4: VSC8151 using CDR as Transmit Timing Source

SONET/SDH Monitoring Circuitry Overview

The monitoring circuitry provides SONET/SDH compliant framing and framing alarms, as well as detect-

ing B1 and B2 parity errors and transport overhead byte output.

Framing

The frame acquisition algorithm determines the in-frame/out-of-frame status of the receiver. Out-of-frame

is defined as a state where the frame boundaries of the received SONET/SDH signal are unknown, i.e. after sys-

tem reset or if for some reason the receiver looses synchronization, e.g. due to ‘bit slips’. In-frame is defined as

a state where the frame boundaries are known.

The receiver monitors the frame synchronization by checking for the presence of a portion of the A1/A2

framing pattern every 125uS. If one or more bit errors are detected in the expected A1/A2 framing pattern out-

put RXFRERR (active high) will be asserted (See Figure 5). If framing pattern errors are detected for four con-

secutive frames a Severely Errored Frame (SEF) alarm will be asserted on output RXSEF (active high) (R5-

223).

Clock and

Data Recovery

2.488Gb/s Data

622Mb/s Data

155MB/s Data

2.488GHz Clock

622MHz Clock

155MHz Clock

Demux &

Monitor

Logic

SEF/LOF ALARMS

Modify

Logic

AIS State

Machine

Mux &

Frame

Assembly

Logic

AIS Insert

Received

Data

CMU

Reference

Generator

AIS Reference

155/78 MHz

AIS Reference

78 MHz

VSC8122

2.488GHz Clock

622MHz Clock

155MHz Clock

RXSIN+/-

RXSCLKIN+/-

TXSOUT+/-

TXSCLKOUT+/-

TXSCLKIN+/-